97
7679H–CAN–08/08
AT90CAN32/64/128
Figure 11-1. T3/T1/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the T3/T1/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T3/T1/T0 has been stable for at
least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is
generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
ExtClk
<f
clk_I/O
/2) given a 50/50 % duty cycle. Since the edge detector uses
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
clk_I/O
/2.5.
An external clock source can not be prescaled.
Figure 11-2. Prescaler for Timer/Counter3, Timer/Counter1 and Timer/Counter0
(1)
Note: 1. The synchronization logic on the input pins (T0/T1/T3) is shown in Figure 11-1.
Tn_sync
(To Clock
Select Logic)
Edge DetectorSynchronization
DQDQ
LE
DQ
Tn
clk
I/O
PSR310
Clear
10-BIT T/C PRESCALER
CK
CK/8
CK/64
CK/256
CK/1024
clk
T1
TIMER/COUNTER1 CLOCK SOURCE
0
CS10
CS11
CS12
T1
clk
T3
TIMER/COUNTER3 CLOCK SOURCE
0
CS30
CS31
CS32
T3
clk
T0
TIMER/COUNTER0 CLOCK SOURCE
0
CS00
CS01
CS02
T0
Synchronization
Synchronization
Synchronization
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