%
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43
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(98/12/10)
Address
Byte Format
3210
Read/WriteDestination
1F039xxx Channel J Data Register, tty20 R/W xxxb
1F03Axxx Channel I Control Register, tty10 R/W xxxb
1F03Bxxx Channel I Data Register, tty10 R/W xxxb
1F03Cxxx Channel L Control Register, tty9 R/W xxxb
1F03Dxxx Channel L Data Register, tty9 R/W xxxb
1F03Exxx Channel K Control Register, tty8 R/W xxxb
1F03Fxxx Channel K Data Register, tty8 R/W xxxb
4. 2. 8. JTAG Interface
The JTAG Interfaces is based on SCANPSC100F National Embedded
Boundary Scan Controller.
It is 8 bits wide parallel interface, and mapped in to 1F0A0000 –
1F0A3FFF address region.
JTAG submodul is compatible with IEEE 1149.1 JTAG Standard Test
Access Port and Boundary Scan Architecture.
Supported National,s SCAN Ease (Embedded Application Software
Enable) Software.
The frequency of PCLK at pin 25 of SPSC100F is 25 MHz.
The JTAG_INT source interrupt is ored with all RS_INT interrupts into
INT_0 summary interrupt.
JTAG Controller Device Codes
Address
Destination Read/Write
Byte Format
3210
1F0A0000 TDO Shifter/Buffer W ---xb
1F0A0000 Counter Register 1 R ---xb
1F0A0004 TDI Shifter/Buffer W ---xb
1F0A0004 TDI Shifter/Buffer R ---xb
1F0A0008 TMS0 Shifter/Buffer W ---xb
1F0A0008 Counter Register 2 R ---xb
1F0A000C TMS1 Shifter/Buffer W ---xb
1F0A000C Counter Register 3 R ---xb
1F0A0010 32-Bit Counter W ---xb
1F0A0010 Counter Register 0 R ---xb
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