%
%
46
&" #"! !$! #
(98/12/10)
Write access stores the upper 4 bits (D7,...,D4) of the transferred byte to the 4Bit–Led–
Register. D3, D2 and D1 control the serial bus lines SDA, SCLK and ACLK.
Bit Allocation of the STATUS Register
D7 D6 D5 D4 D3 D2 D1 D0
Write Leftmost
LED
LED
at front edge
Right-
most
LED
SDA
at J1/B22
SCLK
at J1/B21
ACLK
at J2/B3
Read TMP_IN
T
VME bus
Time out
Device Codes
Address Destination Read/Write
Byte Format
3210
1F05Fxxx STATUS R/W xxxb
1F050xxx SCSIV, -- R xxxb
1F051xxx RSV, ETHV R xxxb
1F052xxx RTCV, KBV R xxxb
1F053xxx CPUV, PRZV R xxxb
4. 2. 11. Interrupt Router
Notes
The processor reaches its 6 interrupt levels by means of the 6 interrupt
inputs, INT_5..INT_0.
INT_5 (highest level) is assigned and hardwired to the floating point in-
terrupt.
The router distributes all onboard and vme bus interrupt sources to level
0 to 4. Source interrupts intended to a certain level are ored to produce
the processor interrupt INT_i. The source interrupts of each level form an
Interrupt Register that can be read via device code providing the status
of that level.
Once activated a source interrupt signal has to keep its level up to being
acknowledged with a special activity like reading an assigned status reg-
ister or the assigned vme interrupt vector.
The router contains only for the temperature interrupt ”TMP_INT” an
interrupt mask. This mask is opened after reset and by writing to the de-
vice code with D1=1 and closed by writing with D1=0.
Routed Source Interrupts
IRQ1..7 7 VME bus interrupts
RS_INT0..5 5 interrupts of 5 individual RS232 subsystems
RS_INT0 is the output of Z85C230, Channel A and B
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