Compaq Deskpro 4000 - List of Tables

Technical Reference Guide
Compaq Deskpro 4000 and 6000 Personal Computers
featuring the Pentium II Processor
First Edition –- October1997
x
LIST OF TABLES
T
ABLE
1–1. A
CRONYMS AND
A
BBREVIATIONS
....................................................................................... 1-3
T
ABLE
2–1. A
RCHITECTURAL
C
OMPARISON
............................................................................................. 2-8
T
ABLE
2–2. S
UPPORT
C
HIPSETS
.......................................................................................................... 2-11
T
ABLE
2–3. G
RAPHICS
S
UBSYSTEM
C
OMPARISON
................................................................................ 2-12
T
ABLE
2–4. E
NVIRONMENTAL
S
PECIFICATIONS
.................................................................................... 2-14
T
ABLE
2–5. E
LECTRICAL
S
PECIFICATIONS
........................................................................................... 2-14
T
ABLE
2–6. P
HYSICAL
S
PECIFICATIONS
............................................................................................... 2-14
T
ABLE
2–7. D
ISKETTE
D
RIVE
S
PECIFICATIONS
..................................................................................... 2-15
T
ABLE
2–8. 8
X
CD-ROM D
RIVE
S
PECIFICATIONS
................................................................................ 2-15
T
ABLE
2–9. S
TANDARD
H
ARD
D
RIVE
S
PECIFICATIONS
......................................................................... 2-16
T
ABLE
3–1. P
ROCESSOR
/M
EMORY
A
RCHITECTURAL
H
IGHLIGHTS
............................................................ 3-1
T
ABLE
3–2. P
ENTIUM
II M
ICROPROCESSOR
B
US
/C
ORE
S
PEED
S
WITCH
S
ETTINGS
.................................... 3-5
T
ABLE
3–3. SW2 B
US
/C
ORE
S
PEED
P
OSITIONS TO
GPIO A
SSIGNMENTS
................................................... 3-5
T
ABLE
3–4. SDRAM P
ERFORMANCE
T
IMES
............................................................................................ 3-6
T
ABLE
3–5. SPD A
DDRESS
M
AP
(SDRAM DIMM)................................................................................. 3-8
T
ABLE
3–6. H
OST
/PCI B
RIDGE
C
ONFIGURATION
R
EGISTERS
(440LX, D
EVICE
0)................................... 3-10
T
ABLE
4–1. PCI B
US
C
ONNECTOR
P
INOUT
............................................................................................ 4-3
T
ABLE
4–2. PCI B
US
M
ASTERING
D
EVICES
........................................................................................... 4-4
T
ABLE
4–3. PCI D
EVICE
C
ONFIGURATION
A
CCESS
................................................................................ 4-6
T
ABLE
4–4. PCI F
UNCTION
C
ONFIGURATION
A
CCES
.............................................................................. 4-7
T
ABLE
4–5. PCI D
EVICE
I
DENTIFICATION
............................................................................................. 4-8
T
ABLE
4–6. PCI/ISA B
RIDGE
C
ONFIGURATION
R
EGISTERS
(82371, F
UNCTION
0).................................. 4-10
T
ABLE
4–7. AGP B
US
C
ONNECTOR
P
INOUT
......................................................................................... 4-11
T
ABLE
4–8. PCI/AGP B
RIDGE
C
ONFIGURATION
R
EGISTERS
(440LX, F
UNCTION
1) ............................... 4-12
T
ABLE
4–9. ISA E
XPANSION
C
ONNECTOR
P
INOUT
............................................................................... 4-14
T
ABLE
4–10. D
EFAULT
DMA C
HANNEL
A
SSIGNMENTS
....................................................................... 4-17
T
ABLE
4–11. DMA P
AGE
R
EGISTER
A
DDRESSES
................................................................................. 4-18
T
ABLE
4–12. DMA C
ONTROLLER
R
EGISTERS
...................................................................................... 4-19
T
ABLE
4–13. M
ASKABLE
I
NTERRUPT
P
RIORITIES AND
A
SSIGNMENTS
.................................................... 4-21
T
ABLE
4–14. M
ASKABLE
I
NTERRUPT
C
ONTROL
R
EGISTERS
.................................................................. 4-21
T
ABLE
4–15. I
NTERVAL
T
IMER
F
UNCTIONS
......................................................................................... 4-24
T
ABLE
4–16. I
NTERVAL
T
IMER
C
ONTROL
R
EGISTERS
........................................................................... 4-24
T
ABLE
4–17. C
LOCK
G
ENERATION AND
D
ISTRIBUTION
........................................................................ 4-25
T
ABLE
4–18. C
ONFIGURATION
M
EMORY
(CMOS) M
AP
....................................................................... 4-27
T
ABLE
4–19. S
YSTEM
I/O M
AP
........................................................................................................... 4-43
T
ABLE
4–20. 87307 I/O C
ONTROLLER
P
N
P S
TANDARD
C
ONTROL
R
EGISTERS
........................................ 4-44
T
ABLE
4–21. S
YSTEM
M
ANAGEMENT
C
ONTROL
R
EGISTERS
................................................................... 4-46