Chapter 4 System Support
Compaq Deskpro 4000 and 6000 Personal Computers
featuring the Pentium II Processor
First Edition - October 1997
4-12
4.3.1 AGP CONFIGURATION
AGP bus operations require the configuration of certain parameters involving system memory
access by the AGP graphics adapter. The AGP bus interface is configured as a PCI device
integrated within the north bridge (82440LX, device 1) component. The AGP function is, from
the PCI bus perspective, treated essentially as a PCI/PCI-type bridge and configured through PCI
configuration registers (Table 4-8). Configuration is accomplished by BIOS during POST.
NOTE:
Configuration of the AGP bus interface involves both device 0 and device 1 of
the 82440LX. Device 0 registers (listed in Table 3-6) include functions that affect basic
control of the AGP. The configuration process of both devices occurs even if the AGP is
not utilized.
Table 4–8.
PCI/AGP Bridge Configuration Registers (82371, Function 1)
Table 4-8.
PCI/AGP Bridge Function Configuration Registers
(82440LX, Function 1)
PCI Config.
Addr. Register
Reset
Value
PCI Config.
Addr. Register
Reset
Value
00, 01h Vender ID 8086h 1Bh Sec. Master Latency Timer 00h
02, 03h Device ID 7181h 1Ch I/O Base Address F0h
04, 05h Command 0000h 1Dh I/O Limit Address 00h
06, 07h Status 02A0h 1E, 1Fh Sec. PCI/PCI Status 02A0h
08h Revision ID 00h 20, 21h Memory Base Address FFF0h
09-0Bh Class Code 22, 23h Memory Limit Address 0000h
0Eh Header Type 01h 24, 25h Prefetch Mem. Base Addr. FFF0h
18h Primary Bus Number 00h 26, 27h Prefetch Mem. Limit Addr. 0000h
19h Secondary Bus Number 00h 3E, 3Fh PCI/PCI Bridge Control 0000h
1Ah Subordinate Bus Number 00h -- -- --
NOTE:
Assume unmarked locations/gaps as reserved. Refer to Intel documentation for detailed
register descriptions.
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