Compaq Deskpro 4000 - 4.5 SYSTEM CLOCK DISTRIBUTION

Technical Reference Guide
Compaq Deskpro 4000 and 6000 Personal Computers
featuring the Pentium II Processor
First Edition–- October 1997
4-25
4.5 SYSTEM CLOCK DISTRIBUTION
The system uses an IC Works W48C67 or compatible part for generation of most clock signals.
Table 4-17 lists the clock signals and to which components they are distributed.
Table 4–17.
Clock Generation and Distribution
Table 4-17.
Clock Generation and Distribution
Signal Source Destination
66, 60 MHz
(CPUCLK) [1]
W48C67 Pentium II, North Bridge,
AGP connector
48 MHz “ South Bridge, 87307
33, 30 MHz
(PCICLK) [2]
“ PCI Slots, South Bridge, TLAN,
SCSI controller
20 MHz “ TLAN3.1 (NIC)
14.31818 MHz Crystal W48C67
14.31818 MHz W48C67 [3] South Bridge, ES1868. ISA slots
8 MHz (BCLK) [4] S. Bridge ISA slots
32 KHz Crystal 87307
NOTES:
[1] Depending on speed configuration (refer to Chapter 3, “Processor/Memory Subsystem”).
[2] PCICLK = CPUCLK/2: 33 MHz if CPUCLK = 66 MHz, 30 MHz if CPUCLK = 60 MHz
[3] Routed through buffer before destination.
[4] BCLK = PCICLK/4: 8.33 MHz if PCICLK = 33 MHz, 7.5 MHz if PCICLK = 30 MHz