Copyright © 2021 congatec GmbH TCTLm02 50/67
Signal Pin # Description I/O PU/PD Comment
DDI2_DDC_AUX_SEL C34 Selects the function of DDI2_CTRLCLK_AUX+ and DDI2_CTRLDATA_AUX-.
This pin shall have a 1M pull-down to logic ground on the module. If this
input is floating, the AUX pair is used for the DP AUX+/- signals. If pulled-
high, the AUX pair contains the CTRLCLK and CTRLDATA signals
I 3.3V PD 1 MΩ
DDI3_PAIR0+
DDI3_PAIR0-
C39
C40
Multiplexed with DP3_LANE0+ and TMDS3_DATA2+
Multiplexed with DP3_LANE0- and TMDS3_DATA2-
O PCIE
DDI3_PAIR1+
DDI3_PAIR1-
C42
C43
Multiplexed with DP3_LANE1+ and TMDS3_DATA1+
Multiplexed with DP3_LANE1- and TMDS3_DATA1-
O PCIE
DDI3_PAIR2+
DDI3_PAIR2-
C46
C47
Multiplexed with DP3_LANE2+ and TMDS3_DATA0+
Multiplexed with DP3_LANE2- and TMDS3_DATA0-
O PCIE
DDI3_PAIR3+
DDI3_PAIR3-
C49
C50
Multiplexed with DP3_LANE3+ and TMDS3_CLK+
Multiplexed with DP3_LANE3- and TMDS3_CLK-
O PCIE
DDI3_HPD C44 Multiplexed with DP3_HPD and HDMI3_HPD I 3.3 V PD 1 MΩ
DDI3_CTRLCLK_AUX+ C36 Multiplexed with DP3_AUX+ and HDMI3_CTRLCLK.
DP AUX+ function if DDI3_DDC_AUX_SEL is no connect.
HDMI/DVI I2C CTRLCLK if DDI3_DDC_AUX_SEL is pulled high
I/O PCIE
I/O OD 3.3 V
PD 100 kΩ
DDI3_CTRLDATA_AUX-
1
C37 Multiplexed with DP3_AUX- and HDMI3_CTRLDATA.
DP AUX- function if DDI3_DDC_AUX_SEL is no connect.
HDMI/DVI I2C CTRLDATA if DDI3_DDC_AUX_SEL is pulled high.
I/O PCIE
I/O OD 3.3 V
PU 100 kΩ
3.3 V
Bootstrap signal (see note below).
DDI enable strap already populated.
DDI3_DDC_AUX_SEL C38 Selects the function of DDI3_CTRLCLK_AUX+ and DDI3_CTRLDATA_AUX-.
This pin shall have a IM pull-down to logic ground on the module. If this
input is floating, the AUX pair is used for the DP AUX+/- signals. If pulled-
high, the AUX pair contains the CTRLCLK and CTRLDATA signals
I 3.3 V PD 1 MΩ
Note
1.
These signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For
more information refer to section 8.2 “Bootstrap Signals”.
Table 18 TMDS Signal Descriptions
Signal Pin # Description I/O PU/PD Comment
TMDS1_CLK +
TMDS1_CLK -
D36
D37
TMDS Clock output differential pair.
Multiplexed with DDI1_PAIR3+ and DDI1_PAIR3-.
O PCIE
TMDS1_DATA0+
TMDS1_DATA0-
D32
D33
TMDS differential pair.
Multiplexed with DDI1_PAIR2+ and DDI1_PAIR2-.
O PCIE
TMDS1_DATA1+
TMDS1_DATA1-
D29
D30
TMDS differential pair.
Multiplexed with DDI1_PAIR1+ and DDI1_PAIR1-.
O PCIE
TMDS1_DATA2+
TMDS1_DATA2-
D26
D27
TMDS differential pair.
Multiplexed with DDI1_PAIR0+ and DDI1_PAIR0-.
O PCIE
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