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Table 19 DisplayPort (DP) Signal Descriptions
Signal Pin # Description I/O PU/PD Comment
DP1_LANE3+
DP1_LANE3-
D36
D37
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI1_PAIR3+ and DDI1_PAIR3-
O PCIE
DP1_LANE2+
DP1_LANE2-
D32
D33
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI1_PAIR2+ and DDI1_PAIR2-
O PCIE
DP1_LANE1+
DP1_LANE1-
D29
D30
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI1_PAIR1+ and DDI1_PAIR1-
O PCIE
DP1_LANE0+
DP1_LANE0-
D26
D27
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI1_PAIR0+ and DDI1_PAIR0-
O PCIE
DP1_HPD C24 Detection of Hot Plug / Unplug and notification of the link layer.
Multiplexed with DDI1_HPD
I 3.3 V PD 1 MΩ
DP1_AUX+ D15 Half-duplex bi-directional AUX channel for services such as link configuration
or maintenance and EDID access.
I/O PCIE PD 100 kΩ
DP1_AUX-
1
D16 Half-duplex bi-directional AUX channel for services such as link configuration
or maintenance and EDID access.
I/O PCIE PU 100 kΩ
3.3 V
Bootstrap signal (see note below).
DP enable strap is already populated.
DP2_LANE3+
DP2_LANE3-
D49
D50
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI2_PAIR3+ and DDI2_PAIR3-
O PCIE
DP2_LANE2+
DP2_LANE2-
D46
D47
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI2_PAIR2+ and DDI2_PAIR2-
O PCIE
DP2_LANE1+
DP2_LANE1-
D42
D43
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI2_PAIR1+ and DDI2_PAIR1-
O PCIE
DP2_LANE0+
DP2_LANE0-
D39
D40
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI2_PAIR0+ and DDI1_PAIR0-
O PCIE
DP2_HPD D44 Detection of Hot Plug / Unplug and notification of the link layer.
Multiplexed with DDI2_HPD
I 3.3 V PD 1 MΩ
DP2_AUX+ C32 Half-duplex bi-directional AUX channel for services such as link configuration
or maintenance and EDID access.
I/O PCIE PD 100 kΩ
DP2_AUX-
1
C33 Half-duplex bi-directional AUX channel for services such as link configuration
or maintenance and EDID access.
I/O PCIE PU 100 kΩ
3.3 V
Bootstrap signal (see note below).
DP enable strap is already populated.
DP3_LANE3+
DP3_LANE3-
C49
C50
Uni-directional main link for the transport of isochronous streams and
secondary data.
Multiplexed with DDI3_PAIR3+ and DDI3_PAIR3-
O PCIE
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