S225-10-5
2-4
Line Drop Compensation, Resistance and Reactance
Settings
Quite often regulators are installed some distance from the the-
oretical load center or the location at which the voltage is
attempted to be regulated. This means the load will not be
served at the desired voltage level due to the losses (voltage
drop) on the line between the regulator and the load.
Furthermore, as the load increases, line losses also increase
causing the lowest voltage condition to occur during the time of
heaviest loading. This is the least desirable time for this to
occur.
To provide the regulator with the capability to regulate at a
“projected” load center, line drop compensation elements are
incorporated on the control. This circuitry consists of a current
source (C.T.), which is proportional to the load current, and
resistive (R) and reactive (X) elements through which this cur-
rent flows. As the load current increases, the resulting C.T. cur-
rent flowing through these elements produces voltage drops
which simulate the voltage drops on the primary line. This caus-
es the “sensed” voltage to be correspondingly altered, there-
fore, the control responds by operating based upon this pseudo
load center voltage.
To select the proper R and X values, the user must know sev-
eral factors about the line being regulated. Cooper Power
Systems has prepared reference document R225-10-1 to assist
in this determination. Once the proper values are determined,
they can be set by simply setting the front panel R & X control
knobs accordingly.
Line Drop Compensation Control Switch
When line drop compensation is used, the correct polarity of the
resistance and reactance elements is necessary for proper reg-
ulation. On four-wire wye connected systems, the polarity selec-
tor is always set for +X and +R values. On delta connected sys-
tems, however, the line current is 30
o
displaced from the lineto-
line voltage (assuming 100% power factor). As a result of this
displacement, the polarity of the appropriate R or X element
must be reversed. The setting of the selector switch may be on
+X+R, -X+R or +X-R settings. The correct polarity determination
is explained in detail in supplement R225-10-1. Note also that
the line drop compensation control switch has an off position to
bypass the compensator circuit entirely. This is convenientfor
test purposes so that the user does not need to disturb the pre-
set R and X values.
CONTROL OPERATION MODES
A selection of three modes in which the control responds to out-
of-band conditions is provided. This permits the user to select
the mode that best fits the application. These modes are
sequential, time integrating, and voltage averaging.
SEQUENTIAL
This is the standard mode of response as shipped from the
factory. When the load voltage goes out-of-band, the time
delay circuit is activated. At the end of the time-out, a tap
change is initiated. After each tap change a two-second
pause occurs to permit the control to sample the voltage
again. This sequence continues until the voltage is brought
into band, at which time the timing circuit is reset. Any time
the voltage goes in-band, the timer is reset.
TIME INTEGRATING
This mode is activated by turning on (sliding upward) dip
switch position #2, as shown in Figure 2-2. When the load
voltage goes out-of-band, the time delay circuit is activated.
At the end of the time out, a tap change is initiated. After
each tap change,
a two-second pause occurs to permit the control to sample
the voltage again. If the voltage is still out-of-band, another
tap change is performed. This sequence continues until the
voltage is brought into band. When the voltage goes in-
band, the timer is decremented at a rate of 1.1 until it reach-
es zero.
VOLTAGE AVERAGING
This mode is activated by turning on (sliding upward) dip
switch position #1, as shown in Figure 2-2. When the load
voltage goes out-of-band, the time delay circuit is activated.
During this time delay period, the microprocessor monitors
and averages the instantaneous load voltage. It then com-
putes the number of tap changes required to bring the aver-
age voltage back to the set voltage level. When the time
delay period is complete, the computed number of tap
changes are performed without any delay between them. A
maximum of five consecutive tap changes will be allowed
before the time delay circuit is reset to avoid an accumula-
tive error. The timer is not reset on voltage excursions in-
band, unless the voltage stays in-band for at least 10 sec-
onds. An error-averaging characteristic is inherent with the
voltage averaging mode.
To permit sufficient time for the microprocessor to average
the voltage, the time delay period must be 30 seconds or
longer. If the time delay is set for less than 30 seconds, the
control reverts to the sequential mode of operation.
If the time integrating and voltage averaging dip switch set-
tings are both in the ON position, the control will revert to the
sequential response mode.
CL-2A CONTROL OPERATION
This section describes the CL-2A regulator control design and
operation. The overall system schematic is shown in Figure 2-
3. This is described in segments to aid in the understanding of
the VR-32 regulator with the CL-2A Control.
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