Dalsa Spyder2 - Page 16

16 Spyder2 User’s Manual
03-032-10091-06 Teledyne DALSA
Table 4: Spyder2 Timing (Fixed Integration Mode)
Symbol Definition Min (ns) Typ
(ns)
Max
(ns)
t w SY N C The minimum low width of the EXSYNC
pulse when not in SMART EXSYNC
mode.
100
t w SY N C
(SM A RT)
* The minimum low width of the EXSYNC
pulse w hen in SM A RT EXSYN C modes to
guar antee the photosites are reset.
2,000
twSYNC_INT The minimum width of the high pulse
w hen the “ SM A RT EXSYN C” featur e i s
turned off
100
twSYNC_INT
(SM A RT)
*
Is the integration time when the “SMART
EXSYN C” feature is available and turned
on. Note that the minimum time is
necessary to guar antee pr oper oper ation.
2,000
tLINE PERIOD
(t
LP
)
The minimum and maximum line times
made up of tTransfer, tREA DOUT pl us
tOVERHEAD to meet specifications.
54, 054 (2K)
28, 248 (1K)
15, 313 (512)
10
6
tTransfer The time fr om the r eception of the f al li ng
edge of EXSYN C to the r i si ng edge of
LVA L w hen pretri gger is set to zero.
Pr etrigger r ed uces the number of clocks to
the rising edge of LVA L but d oesn’t
change the time to the first valid pixel. If
the fi xed integrati on time mod e of
operation is avai l able and sel ected then
the integration time is added to the
specified value.
1,420 +/ -50
tw Fixed Int. Fi xed Integration Ti me mode of operati on
for v ar i able exsync fr equency.
800 t
LP
–
2,000
tREADOUT I s the number of pixels per tap ti mes the
readout clock period. Pretrigger = 0.
51,200 (2K)
25,600 (1K)
12,800 (512)
tOVERHEA D Is the number of pixels that must elapse
after the falli ng edge of LVA L bef ore the
EXSYN C signal can be asserted . Thi s ti me
is used to clamp the internal analog
electronics
540+/ -50
thPR A ppl ies w hen the PRIN exposure contr ol
feature i s enabl ed . The PRI N si gnal must
be held a minimum time after the
EXSYNC falling edge to avoid losing the
integrated charge
0
tw PR_LOW M i nimum Low time to assur e complete
photosi te r eset
2,000 +/ - 200
t PR_SET The nominal time that the photo sites are
integrating. Clock synchronization will
lead to integration time jitter, which is
shown in the specification as +/ - values.
The user should command times gr eater
than these to ensure proper charge
2,000+/ -200