W9864G6KH-5 (HDMI : U1023)
W9864G6KH-5 Pin description
W9864G6KH
Publication Release Date: Nov. 12, 2013
- 4 - Revision A02
4. PIN CONFIGURATION
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
LDQM
CAS
RAS
CS
BS 0
BS 1
A10/ AP
A0
A1
A2
A3
DQ 15
DQ 14
DQ 13
DQ 12
DQ 11
DQ 10
DQ 9
DQ 8
NC
UDQ M
CL K
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VDDQ
VDDQ
VS SQ
VS SQ
VDD
VDD
VSS
VS SQ
VSSQ
VDDQ
VSS
VSS
WE
VDD
VDDQ
W9864G6KH
Publication Release Date: Nov. 12, 2013
- 5 - Revision A02
5. PIN DESCRIPTION
PIN NUMBER PIN NAME FUNCTION DESCRIPTION
23 ~ 26, 22,
29 ~35
A0 A11
Address
Multiplexed pins for row and column address.
Row address: A0
A11. Column address: A0 A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank
selected by BS0, BS1.
20, 21
BS0, BS1 Bank Select
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
2, 4, 5, 7, 8, 10,
11, 13, 42, 44,
45, 47, 48, 50,
51, 53
DQ0 DQ15
Data
Input/ Output
Multiplexed pins for data output and input.
19
CS
Chip Select
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
18
Row Address
Strobe
Command input. When sampled at the rising edge of
the clock
,
CA
and
WE
define the
operation to be executed.
17
CAS
Column
Address Strobe
Referred to
16
WE
Write Enable
Referred to
39, 15
UDQM
LDQM
Input/output
mask
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
38 CLK Clock Inputs
System clock used to sample inputs on the rising
edge of clock.
37 CKE Clock Enable
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
1, 14, 27 VDD Power Power for input buffers and logic circuit inside DRAM.
28, 41, 54 VSS Ground
Ground for input buffers and logic circuit inside
DRAM.
3, 9, 43, 49 VDDQ
Power for I/O
buffer
Separated power from VDD, to improve DQ noise
immunity.
6, 12, 46, 52 VSSQ
Ground for I/O
buffer
Separated ground from VSS, to improve DQ noise
immunity.
36, 40 NC No Connection No connection.
152
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