Denon DCD-1500AE - M30625 FGNGP IC Pin Assignment

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DCD-1500AE
M30625FGPGP (SM: IC739)
Pin Assignment
M30625FGNGP Port Assignment
pin port function I/O Initial mode action NOTE
1VREF
2AVCC
3 P97/ADTRG~/SIN4 P97 O L OPEN DIR_RST2
4 P96/ANEX1/SOUT4 SOUT4 O L FDAT DISPLAY DATA for FL DRIVER
5 P95/ANEX0/CLK4 CLK4 O L FCLK DISPLAY CLOCK for FL DRIVER
6 P94/DA1/TB4IN P94 O L DSRST1 RESET for DAC (DSD1791)
7 P93/DA0/TB3IN P93 O H GAL_RST RESET for GAL16V8
8 P92/TB2IN/SOUT3 P92 O L OPEN OPEN
9 P91/TB1IN/SIN3 P91 I H USER1 MODEL SELECT 1 (10k P.U)
10 P90/TB0IN/CLK3 P90 O L OPEN DL_ON P.DN only
11 P14_1 O L OPEN OPEN
12 P14_0 O H DSCS1 CHIP SELECT for DAC (DSD1791)
13 BYTE BYTE I BYTE PULL UP(8bit)
14 CNVss CNVss I CNVSS PULL DOWN (5.6k ohm)
15 P87/XCIN P87 O L OPEN CD_SEL (INTERNAL CD PLAY ONLT "H")
16 P86/XCOUT P86 O H OPEN DSD_NORM (NORMAL DSD MODE ONLY "H")
17 RESET~ RESET~ I RESET RESET INPUT
18 XOUT XOUT O X.TAL OSC OUT
19 VSS VSS - VSS GND
20 XIN XIN I X.TAL OSC IN
21 VCC VCC - 3.3V POWER INPUT
22 P85/NMI~ P85 I P_UP1 10K PULL UP(NON CONECT) NOT USE
23 P84/INT2~ INT2~ I IR_IN IR INPUTSIGNAL (SHARP FORMAT)
24 P83/INT1~ INT1~ I MINT INT from CXD1885Q
25 P82/INT0~ INT0~ I DRVIRQ CXD1885Q DATA REQUEST
26 P81/TA4IN/U~ P81 I H OPEN
DL_IDD (DL ID WRITE MODE DETECTION ("L":Write Mode)
27 P80/TA4OUT/U TA4OUT O L PWM TRAY CONTROL PWM SIGNAL
28 P77/TA3IN P77 O H SELDSD SELECT for DSD SIGNAL(PLD)
29 P76/TA3OUT P76 O H SMUTE MUTING for CXD2753R
30 P75/TA2IN/W~ P75 O H DSDRST RESET for CXD2753R
31 P74/TA2OUT/W P74 I MSREADY SERIAL DATA READY from CXD2753R
VREF AVCC
P97/ADTRG/SIN4 P96/ANEX1/SOUT4
P95/ANEX0/CLK4
P94/DA1/TB4IN P93/DA0/TB3IN
P92/TB2IN/SOUT3
P91/TB1IN/SIN3 P90/TB0IN/CLK3
P141 P140
BYTE
CNVss
P87/XCIN
P86/XCOUT
RESET
XOUT
VSS XIN VCC
P85/NMI
P84/INT2 P83/INT1 P82/INT0
P81/TA4IN/U P80/TA4OUT/U
P77/TA3IN
P76/TA3OUT
P75/TA2IN/W P74/TA2OUT/W
P73/CTS2/RTS2/TA1IN/V
P72/CLK2/TA1OUT/V
P71/RXD2/SCL/TA0IN/TB5IN
P70/TXD2/SDA/TA0OUT
P67/TXD1
VCC
P66/RXD1
P125
P126
P127
P50/WRL/WR
P51/WRH/BHE
P52/RD
P53/BCLK
P130
P131
P132
P133
P54/HLDA
P55/HOLD
P56/ALE
P57/RDY/CLKOUT
P134
P135
P136
P137
P60/CTS0/RTS0
P61/CLK0
P62/RXD0
P63/TXD0
P64/CTS1/RTS1/CTS0/CLKS1
P65/CLK1
VSS
P11/D9 P12/D10 P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 P20/A0(/D0/‑) P21/A1(/D1/D0) P22/A2(/D2/D1) P23/A3(/D3/D2) P24/A4(/D4/D3) P25/A5(/D5/D4) P26/A6(/D6/D5) P27/A7(/D7/D6) VSS P30/A8(/‑/D7) VCC P120 P121 P122 P123 P124 P31/A9 P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 P42/A18 P43/A19 P44/CS0 P45/CS1 P46/CS2 P47/CS3
P10/D8
P07/D7
P06/D6
P05/D5
P04/D4
P03/D3
P02/D2
P01/D1
P00/D0
P117
P116
P115
P114
P113
P112
P111
P110
P107/AN7/KI3
P106/AN6/KI2
P105/AN5/KI1
P104/AN4/KI0
P103/AN3
P102/AN2
P101/AN1
AVSS
P100/AN0