Denon DCD-1500AE - Page 32

32
DCD-1500AE
Ipu: Pull-up input Ipd: Pull-down input Ai: Analog input
88 P27/A7(/D7/D6) A7 O A7 ADRRES LINE
89 P26/A6(/D6/D5) A6 O A6 ADRRES LINE
90 P25/A5(/D5/D4) A5 O A5 ADRRES LINE
91 P24/A4(/D4/D3) A4 O A4 ADRRES LINE
92 P23/A3(/D3/D2) A3 O A3 ADRRES LINE
93 P22/A2(/D2/D1) A2 O A2 ADRRES LINE
94 P21/A1(/D1/D0) A1 O A1 ADRRES LINE
95 P20/A0(/D0/-) A0 O A0 ADRRES LINE
96 P17/D15/INT5~ P17 O L OPEN IIC CLK FOR EE_ROM(AT24C04N)
97 P16/D14/INT4~ P16 I/O H OPEN IIC DATA FOR EE_ROM(AT24C04N)
98 P15/D13/INT3~ P15 I (L) OPEN DIR_INT
99 P14/D12 P14 I OPN_SW TRAY OPEN DETECT SW (P.U)
100 P13/D11 P13 I CLS_SW TRAY CLOSE DETECT SW (P.U)
Flash(w:pull up)
101 P12/D10 P12 I FILTI NOT USE(10k P/U) (Low:384fs/Hi:192fs)
102 P11/D9 P11 O L OPEN EXT/INT
103 P10/D8 P10 O H A_MUTE MUTING (H:MUTE) RELAY/TR
104 P07/D7 D7 I/O D7 8bit DATA LINE
105 P06/D6 D6 I/O D6 8bit DATA LINE
106 P05/D5 D5 I/O D5 8bit DATA LINE
107 P04/D4 D4 I/O D4 8bit DATA LINE
108 P03/D3 D3 I/O D3 8bit DATA LINE
109 P02/D2 D2 I/O D2 8bit DATA LINE
110 P01/D1 D1 I/O D1 8bit DATA LINE
111 P00/D0 D0 I/O D0 8bit DATA LINE
112 P11_7 I (L) OPEN DIR_DO
113 P11_6 O H DSDI DSD_DI
114 P11_5 O DXP_CS CHIP SELECT for DXP6001
115 P11_4 O L DXP_RST RESET for DXP6001
116 P11_3 O DXP/DSD_MDT DATA for DXP6001/DSD1791
117 P11_2 O DXP/DSD_MCK DATA_CLOCK for DXP6001/DSD1791
118 P11_1 O L OPEN RST2
119 P11_0 O L OPEN
DSD/PCM
120 P107/AN7/KI3~ P107 O H MODE CD/SACD SWITCHING SIGNAL(L:CD,SACD:H)
121 P106/AN6/KI2~ P106 O L FCS DISPLAY CHIP SERECT for FL DRIVER
122 P105/AN5/KI1~ P105 O H OPEN SM5819 INPUT SWITC (H,EXTSERECT)
123 P104/AN4/KI0~ P104 O L OPEN DSD1792 RST
124 P103/AN3 P103 O L FRRST DISPLAY DRIVER RESET
125 P102/AN2 AN2 I KEY2 KEYS SENS
126 P101/AN1 AN1 I KEY1 KEYS SENS
127 AVSS AVSS - GND AD GND
128 P100/AN0 AN0 I KEY0 KEYS SENS
pin port function I/O Initial mode action NOTE