Eaton EDR-5000 - Page 816

EDR-5000 IM02602007E
If no signal is assigned to a logic gate (All inputs are "0"), then the output of the gate will be set as follows:
"0" for an AND gate
"1" for a NAND gate
"0" for an OR gate
"1" for a NOR gate
If at least one input signal is assigned to a gate all not assigned inputs are set to:
"1" for AND / NAND gates
"0" for an OR / NOR gates
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