Eaton EDR-5000 - Page 817

EDR-5000 IM02602007E
Detailed Overview – Overall Logic Diagram.
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φ
AND
OR
NAND
NOR
t-On Delay
t-Off Delay
Gate Out
Timer Out
Out
Out inverted
Delay Timer
1..n, Assignment List
LE[x].IN1
Active
Inactive
Inverting1
XOR
1..n, Assignment List
LE[x].IN2
Active
Inactive
Inverting2
XOR
1..n, Assignment List
LE[x].IN3
Active
Inactive
Inverting3
XOR
1..n, Assignment List
LE[x].IN4
Active
Inactive
Inverting4
XOR
1..n, Assignment List
LE[x].Reset Latched
Active
Inactive
Inverting Reset
XOR
Gate AND
OR
NAND
NOR
Active
Inactive
Inverting Set
XOR
S Q
R Q
LE[1]...[n]