PROTEUS user manual
Issue C
70
CPLD pin mapping
Some of GPIO pins are controlled through CPLD. Control these pins use register
mapped to I/O address 0x5A. Other registers can be found on 0x5B and 0x5C. See
following tables with detailed description.
Address: 0x5A (Read/Write)
Bit Description Note
0 GPIO0 Data Connected to J22
pin B35
1 GPIO1 Data Reserved
2 GPIO0 Direction 1 – Output / 0 – Input
3 GPIO1 Direction 1 – Output / 0 – Input
4 GPIO0 Enable 1 – Enabled / 0 - Disabled
5 GPIO1 Enable 1 – Enabled / 0 - Disabled
6 - Reserved
7 - Reserved
Address: 0x5B (Read only)
Bit Signal Description
0 COM_THRM# Connected to J22 pin B35
1 - Reserved
2 - Reserved
3 - Reserved
4 - Reserved
5 - Reserved
6 - Reserved
7 LVDS_OC# LVDS A or B display power over current flag
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