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FIBOCOM L850-GL Series Hardware Guide Page 29 of 59
+3.3V
PERST#
RESET#
Module State
InitializationActivation
FCPO#
typical 10s
Activation
t
off
Finalization OFF
AT+CFUN=0
t
off2
t
off1
t
on1
t
on2
t
sd
Figure 3-9 Reset timing 2
nd
Index Min. Recommended
Comments
t
off1
16ms
20ms
RESET# should be asserted after PERST#,
refer section 3.3.2
t
off2
2ms 10ms
FCPO# should be asserted after RESET#,
refer section 3.3.2
t
off
500ms 500ms
Time to allow the WWAN module to fully discharge any
residual voltages before the pin could be de-asserted
again. This is required for both Pre-OS as well as Runtime
flow
t
on1
8ms 20ms
RESET# should be de-asserted after FCPO#,
refer section 3.3.1.2
t
on2
50ms 100ms
The time delay of PERST# de-asserted after FCPO#,
PERST# must always be the last to get de-asserted.
refer section 3.3.1.2
Note
：
When USB is used as data transfer interface, follow timing above in PERST# connecting with
host, otherwise don’t control PERST# in PERST# floating condition.
3.3.4 PCIe Link State
Modem has the lowest power consumption in D0 L1.2 PCIe link state. D3
cold
L2 will increase extra about
0.5mA power consumption. CLKREQ# can assert or de-assert in D3
cold
L2, but CLKREQ# shouldn’t be
changed again during D3
cold
L2. When CLKREQ# asserts in D3
cold
L2, it will increase extra 0.3mA power
consumption compared with CLKREQ# de-asserted in D3
cold
L2. We recommend keep CLKREQ# de-
asserted in D3
cold
L2.
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