2-10
Serial-data
CLK
LATCH (ST)
While data and clock are sent from CPU, changed data is taken in by LATCH signal.
Figure 2-4 Transmission Timing
M54972P (8BIT SERIAL INPUT LATCHED DRIVER)
Q
LD
D Q
T
EN
Enable input
LATCH
Latch input
Sin
Serial data input
T
clock
O1
S out
serial output
Q
LD
D Q
T
O2
Q
LD
D Q
T
O3
Q
LD
D Q
T
O4
Q
LD
D Q
T
O5
Q
LD
D Q
T
O6
Q
LD
D Q
T
O7
Q
LD
D Q
T
O8
Vcc
power P-GND
Driver GND
4
7
6
2
1
3
16 15 14 13 10 9
5
8
12 11
Figure 2-5 Block Diagram of M54972P
M54972P consists of 8 D-flip-flops and 8 latches connected to the outputs of the flip-
flops. Serial-data signals input to the serial-data input (S-in) and clock pulses input to the
clock input (T). Every time the clock changes from L to H, the input signal is taken in the
internal shift register and the data in the shift register shifts successively.
The serial output (S-out) is connected to the serial input (S-in) of the next M54972P,
when more than one M54972P are connected in series to increase bit number.
The data in the shift register output to the parallel output Q1 to Q8, when the latch input
(LATCH) is H, the enable input for output control (EN) is L, and the clock changes from
L to H.
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