Furuno FS-1503 - Block Diagram of Synthesizer Circuit

2-14
Loop Filter
VCO
Ref. OSC 36 MHz
(
Band selection
)
DDS
Comp. Divider (N = 54 to 84)
Ref. Divider (M = 6)
Phase Comparator
FL 502
6 MHz
1/2
LATCH
C554
U506
OVEN
S.DATA
S.CLK
U501 (AD7008AP20)
1Lo
2Lo
3Lo
Fo = F + 54.455M + OFF SET
54M
453.5 to 456.9 kHz
(54.555 to 84.45499 MHz)
U503
From CPU
LD
CLK
PLL1 ENB
DATA
Unlock (See note)
U502
18 MHz
1 MHz
Q501-2
4
×
2 ??
Output of DDS is used as a reference frequency of PLL. Frequency data changes the reference frequency to produce 1Lo signal.
(6 MHz: DDS Output Freq.) × N
1Lo Freq. =
M
Freq. Data
VCO BAND data
Note) When the CPU receives "Unlock" Signal from PLL IC U502 or U504, TX and RX are disabled and frequency indication blinks.
Phase Accumulator
ROM Look-up Table
D/A
FIL
Ref. CLK
Freq. Select Data
OUTPUT
Simplified DDS Block Diagram
LOAD
FL 501
Loop Filter VCO
Comp. Divider (N = 4535 to 4569)
Ref. Divider (M = 1800)
Phase Comparator
10 kHz
C539/R537
DATA
LD
CLK
PLL3 ENB
CLK
ST SYN
DATA
Q1 to 5
U504
1/100
U505
Freq. Adjuster
Q516
Y501
Q510 to 512
Q513
Q508
TP506
(6 MHz)
TP507
TP502
TP505
TP503
U507/Q515
12V
Q509
* Depending on class of emission
* Depending on class of emission
S.DATA
S.CLK LOAD
CLK
PLL1 ENB
DATA
ST SYN PLL3 ENB
(18 MHz)
(36 MHz)
(MC145170D1)
(MC145170D1)
(M54972)
(M54459L)
(MB511)
(6 MHz)
DDS RESET
Q6
DDS RESET
Q506
Q505
Figure 2-7 Block Diagram of Synthesizer Circuit