GE MiCOM P141 Agile - Page 22

Figure 39: Modification of current pickup level for voltage restrained overcurrent protection 106
Figure 40: Voltage dependant overcurrent logic (Phase A to phase B) 107
Figure 41: Selecting the current threshold setting 109
Figure 42: Cold Load Pickup logic 111
Figure 43: Selective Logic 113
Figure 44: Selecting the timer settings 115
Figure 45: Negative Sequence Overcurrent logic - non-directional operation 117
Figure 46: Composite Earth Fault Start Logic 117
Figure 47: Negative Sequence Overcurrent logic - directional operation 118
Figure 48: Non-directional EF logic (single stage) 121
Figure 49: IDG Characteristic 122
Figure 50: Directional EF logic with neutral voltage polarization (single stage) 123
Figure 51: Directional Earth Fault logic with negative sequence polarisation (single stage) 124
Figure 52: Current level (amps) at which transient faults are self-extinguishing 125
Figure 53: Earth fault in Petersen Coil earthed system 125
Figure 54: Distribution of currents during a Phase C fault 126
Figure 55: Phasors for a phase C earth fault in a Petersen Coil earthed system 126
Figure 56: Zero sequence network showing residual currents 127
Figure 57: Phase C earth fault in Petersen Coil earthed system: practical case with resistance
pr
esent
128
Figur
e 58: Non-directional SEF logic 130
Figure 59: SEF Any Start Logic 131
Figure 60: EPATR B characteristic shown for TMS = 1.0 132
Figure 61: Types of directional control 132
Figure 62: Resistive components of spill current 133
Figure 63: Operating characteristic for Icos 134
Figure 64: Directional SEF with VN polarisation (single stage) 135
Figure 65: Current distribution in an insulated system with C phase fault 136
Figure 66: Phasor diagrams for insulated system with C phase fault 137
Figure 67: Positioning of core balance current transformers 138
Figure 68: Thermal overload protection logic diagram 140
Figure 69: Spreadsheet calculation for dual time constant thermal characteristic 141
Figure 70: Dual time constant thermal characteristic 141
Figure 71: Broken conductor logic 144
Figure 72: Blocked Overcurrent logic 146
Figure 73: Blocked Earth Fault logic 147
Figure 74: Simple busbar blocking scheme 147
Figure 75: Simple busbar blocking scheme characteristics 148
Figure 76: 2nd Harmonic Blocking Logic (POC Input) 150
Figure 77: 2nd Harmonic Blocking Logic (SEF Input) 151
Table of Figures P14x
xx P14xEd1-TM-EN-1