GE P54E - Page 759

P54A/B/C/E
Appendix B - Settings and Signals
P54xMED-TM-EN-1
B193
MENU TEXT COL ROW DEFAULT SETTING AVAILABLE OPTIONS
DESCRIPTION
Bus is considered Live with voltage above this setting.
Live Bus 1 48 87 32
From 5 to 132 in steps of 0.5
[Courier Number (voltage)]
Bus 1 is considered Live with voltage above this setting.
Dead Bus 48 88 13
From 5 to 132 in steps of 0.5
[Courier Number (voltage)]
Bus is considered Dead with voltage below this setting.
Dead Bus 1 48 88 13
From 5 to 132 in steps of 0.5
[Courier Number (voltage)]
Bus 1 is considered Dead with voltage below this setting.
Live Bus 2 48 89 32
From 5 to 132 in steps of 0.5
[Courier Number (voltage)]
Bus 2 is considered Live with voltage above this setting.
CS OV 48 8C 130
From 60 to 200 in steps of 0.5
[Courier Number (voltage)]
Check Synch Overvoltage setting decides that System Check Synchronism logic for CB1 is blocked if V> is one of the selected options in
setting CB1 CS Volt.Blk (48 8E), and either line or bus voltage is above this setting.
System Check Synchronism for CB2 is blocked if V> is one of the selected options in setting CB2 CS Volt. Blk (48 9C), and either line or bus
voltage is above this setting.
System Checks 48 8D Disabled
Disabled
Enabled
[Indexed String]
Setting to enable or disable both stages of system checks for reclosing.
If System Checks is set to Disabled, all other menu settings associated with synchronism checks become invisible, and a DDB (880) signal
SysChks Inactive is set.
Sys Checks CB1 48 8D Disabled
Disabled
Enabled
[Indexed String]
Setting to enable or disable both stages of system checks for reclosing CB1
If Sys Checks CB1 is set to Disabled, all other menu settings associated with synchronism checks for CB1 become invisible, and a DDB (880)
signal SChksInactiveCB1 is set.
CS Voltage Block 48 8E V<
None
V<
V>
Vdiff>
V< and V>
V< and Vdiff>
V> and Vdiff>
V< V> and Vdiff>
[Indexed String]
Setting to determine which, if any, conditions should block synchronism check (undervoltage V<, overvoltage V>, and/or voltage differential
Vdiff etc) for the line and bus voltages.
CB1 CS Volt. Blk 48 8E V<
None
V<
V>
Vdiff>
V< and V>
V< and Vdiff>
V> and Vdiff>
V< V> and Vdiff>
[Indexed String]
Setting to determine which, if any, conditions should block synchronism check for CB1 (undervoltage V<, overvoltage V>, and/or voltage
differential Vdiff etc) for the line and bus voltages.
CS1 Status 48 8F Enabled
Disabled
Enabled
[Indexed String]
Setting to enable or disable the stage 1 synchronism check elements for auto-reclosing and manual closing of CB.
CB1 CS1 Status 48 8F Enabled
Disabled
Enabled
[Indexed String]
Setting to enable or disable the stage 1 synchronism check elements for auto-reclosing and manual closing CB1.