HP 54501A - Page 68

HP 54501A SERVICE
Trigger Comparator . The
trigger comparator
compares the input signal
from the
preamplifier with the
trigger level signal from
the DAC . The
comparator also uses the trig-
ger
hysteresis from the DAC
for partial noise
immunity to the system .
The incoming signal
must be large enough
to satisfy the hysteresis
requirement before
the output of the compara-
tor switches .

The output of the
trigger com-
parator goes to the logic
trigger .
Logic Trigger . The user
trigger information is
programmed to the logic
trigger . The logic
trigger accepts the
outputs of all four trigger
comparators and
may be programmed
for
complex
triggering on any one or
all four
channels .
Timebase . The
timebase is the IC that
provides the
sample clock for all timing neces-
sary for data
acquisition . The clock for the
timebase
is a 40 MHz oscillator . The
timebase
uses
the 40 MHz time and
the
40
MHz divided
by four
(10 MHz) . The timebase
has
program-
mable internal dividers for
output frequencies
of the
sample clock appropriate
for the time
range the user has selected .
The timebase
receives the trigger timing
information from the
fine interpolator .
The timebase
has counters to
control how
much
data is taken before
(pretrigger data) and
after (posttrigger data)
the trigger event . When
the desired number of
points for pretrigger
data
have occurred,
the timebase sends a sig-
nal to the logic trigger
(trigger arm) indicating
it is ready for
the trigger event to occur
.
As
soon as the
trigger condition is
satisfied, the
logic trigger
sends a signal back to
the
timebase .
The timebase then begins
counting
down the
posttrigger delay counter
. When the
countdown
reaches zero, the
sample clocks to
the
memory address counters
are stopped and
the 68000
is signaled that
the acquisition is
complete .
Fine Interpolator
. The fine interpolator is a
dual-slope
interpolator circuit that acts as a
time-interval
stretcher to supply the trigger
timing information
to the timebase . When
the
logic trigger
receives a signal that meets the
programmed
triggering requirements, it signals
the timebase .
The timebase then sends a
pulse to
the fine interpolator . The pulse is
equal in width to the time between the trigger
and the next
sample
clock
.

The fine
interpolator
stretches this time - out by a factor
of 250 .
Meanwhile, the timebase runs a
counter (off the 40 MHz oscillator) until the
fine interpolator indicates
the stretch
is
com
plete .

These are the sample points stored by
the
timebase for the 68000 to use for display-
ing the acquireddata .
D/A
Converter . The digital-to-analog converter
(DAC) has 16 outputs and is programmed to
set the levels for channel DC
offset, trigger
level, trigger hysteresis,
and levels going to the
A/D converter
. The highest level out of the
DAC
is 5
V dc, and the lowest is 0 V dc .

The
voltages between those two levels are pulses
from 0 to 5 V, varying in width . The DAC out-
puts go through op amp filters to
convert the
pulse streams to do
levels
.
The do levels are
then applied to the appropriate
circuits .
Acquisition RAM
. The acquisition memory is
2K X 8 bits of
RAM .
The sample
clock from the timebase is gated
with digital circuitry and some of
the control
lines and applied to
memory address counters
of the acquisition
RAM . The memory address
counters
step through the address locations of
RAM and
their rate is the rate data is acquired .
When the 68000 is signalled by the
timebase
that the data acquisition is
complete, the data
is then transferred to
the system RAM .
The data stored in system
RAM is the data
from the A/D converters
interleaved with the
interpolation
information stored by the
timebase .
The 68000
retrieves the data from memory
(system RAM) to
display on the CRT monitor
.
The timing information of
the trigger event
relative to the sample clock is
the data from
the timebase . The 68000 uses
this data for
placing the sample points at
the correct loca-
tions on the display .