HP 54501A - System Control

6-11 . System
Control
The system control of
the HP 54501A consists
of
a 68000 microprocessor
and the associated
circuitry required to
control the acquisition
section of
the System Board Assembly and
the
display monitor . The
interfaces for HP-IB and
keyboard
assemblies are also included on
the
system board
. Figure 6-3 is
the
block
diagram
for system
control of the HP 54501A .
Central Processing Unit (CPU)
The CPU for
the
HP
54501A is the 68000 P10
microprocessor
with addressing capability of
16 Megabytes
(23 address lines/16 data lines) .
The
CPU receives its clock from the TCL
(Timing Control Logic) at
the rate of 9 .8304
MHz (10 MHz creating
a cycle time of 101 .7
nanoseconds (100
nsec) . TCL provides all
timing for the CPU
including timing control of
bus arbitration .
Therefore, the bus grant out-
put from the CPU is
not used . The CPU drives
the read/write
line and the address and data
strobes .
The CPU activates
a free-running 1 MHz
en-
able clock
for synchronization
with the CRT
Controller
(CRTC) . The TCL generates
the
Valid
Peripheral address signal on
behalf of the
CRTC
to complete the
peripheral control
timing .
Power . System
control
of
the HP 54501A
requires +5 volts do
(relative to digital ground)
and +12 volts do
(relative to display ground) for
operation . System
control supplies the display
board
with +5 volts, +12 volts, display ground
and
digital ground .
The beeper/clicker circuit
is operated
off the +12 display voltage, the
remaining system
control circuitry is operated
from the +5
digital voltage .
Clock . The
fundamental clock period for sys-
tem control is
derived from a 19 .668 MHz (20
MHz) crystal
oscillator . The fundamental sys-
tem control clock is
multiplexed and dis
tributed to provide
synchronization for the
timing control logic
(TCL), the dot rate for the
display
circuitry, and a
high-frequency signal
to data acquisition
for the AC Calibrator
Output signal on
the rear panel .
Timing Control Logic (TCL) .
HP 54501
A SERVICE
Timing
Control Logic (TCL) is reponsible for
providing
timing and control for System
Control of the HP 54501A .
The TCL
circuitry consists of PALs (program-
mable array logic), various logic gates, LRC
delay circuit, and miscellaneous
circuitry for
arbitrating between display
and refresh
requests for display
and
system
RAMs . The
PALs and
arbitrator circuitry and are
synchronized
with the 20 MHz clock, while the
LCR
delay circuit and miscellaneous gates are
asynchronous .
The signals generated by TCL include a
hardware select
line to the decoders, write-
enable
to protected non-volatile Static RAM,
and all timing and control signals for the inter-
face circuits .
Beeper/Clicker . The beeper/clicker is the
sound effect for the
HP
54501A
. The beeper is
not utilized by
the HP 54501A . The clicker
sounds
when warning or error messages are
displayed, when a key on the keypad is
pressed and when
the RPG
is
rotated .
The 3 kHz square
wave required by the clicker
for operation is
provided by the CRT
Controller
.
The clicker
may be deactivated via the UTILITY
menu .
Reset/Preset . The reset/preset circuitry con-
sists of a voltage divider,
reference voltage,
and comparator
to provide the System Board
Assembly with a timeout during power up and
power down of the HP 54501A . This
timeout
signal is applied to critical time and
power
sensitive ICs on the board . The
signal
goes
to
the microprocessor, the TCL, decoders, and
HP-113 and data acquisition interfaces .
When power is applied, as the +5
V supply
crosses
the
upper
threshold of the comparator,
the timeout
signal of approximately 200 mil-
liseconds is
generated and applied to the sys-
tem
control circuitry assuring the board
powersup
in a known state .