1
I
Theory of Operation
Processor Board Description
This information deals with schematics lA to lE.
Clock Generator (U107, U110)
UI07 generates a 16MHz clock signal (CLK16). This is divided by 2
and 4 by U110, to generate the 811Hz clock signal (CLK8) and the
4MHz clock signal (CLK4).
CLK16 is used as the clock for the display Gate Array,
CLK4 clocks the HP-IB interface circuit (schematic lD).
CLK8 is used to clock the Processar UlOl, the PAL Ul06 and the
Device Bus interface circuits (schematic lC).
Reset Circuit (U109) with Buffers (U104)
Ul09 senses the +5 Volt supply voltage during power up.
Until the supply voltage comes above approximately 4.8 Volts, Ul09
activates the reset signal. When the threshold value is reached , the
reset is removed, after a short delay, and the correct start conditions
are established on the processor board.
In the case of a supply voltage drop during normal operation, or if
the supply voltage is switched off, a power down reset signal (LPOR)
is generated which stops further signal processing, switches off the
address decoder and turns on the battery supply for the real time
clock and battery buffered RAMs.
The CPU (UlOl) is a 16/32 bit processor with an 8 bit data bus.
Signals LAS /LDS from the CPU indicate/ confirm that
addresses/ data are ready for execution.
The interface control circuit (Ul03, Ul04) generates the readj'write
signals far the memories and interface circuits. These memories and
interface circuits are seIected by the address decoder Ul05.
Due to the different access times for memories and interface circuits,
the data acknowledge must be delayed to synchronize the memories
and interface circuit to the CPU. This is done by the PAL (Ul06).
CentraI Processor Unit (U101) with PAL (U106), Address Decoder (U105) and Interface
Contro I (U103, U104)
Theory of Operation 1-1
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