U50l delays the clock, CLK8, by 4 cycles to ensure that data and
addresses are valid in the Module.
The bidirectional buffer U505 buffers the data to and from the
Module. U504 is used to test the data bus to the modules during the
selftest. Data are written from the microprocessor via U504 into a
register in a module's FACE gate array and then read back via U505.
HP-IB, Real Time Clock and InterfacejClock Selection
This information deals with schematic lD.
HP-IB
U402 is the HP-IB controller. Data is transferred to and from the
CPU via datalines PDO to PD7. There are eight read only and eight
write only registers on the controller. These are selected by address
lines PA1, PA2 and PA3, in conjunction with the readjwrite signal
HREAD. The data lines, IDIOl to IDI08, are fed to the HP-IB
connector via the bidirectional buffer U403 and the mother board.
IDAV, INRFD and INDAC provide the three-line handshake between
the HP-IB and the HP-IB controller. IATN, ISRQ, IREN, IIFC and
IEOI are used to manage the fìow of data over the interface bus. AH
the eight of these signals are buffered by TJ404.
Real Time Clock
The clock IC U406 is crystal controlled. It has both time and date
functions. The clock is also used to determine the measurement time
in stability applications. It generates interrupt (LRTCI) every l6ms.
This forces the microprocessor, via the KID U60l (schematic lE),
to jump to an interrupt service routine. When no clock function is
required, the microprocessor ignores this interrupt.
InterfacejClock Selection
The interfaces and real time clock are selected by U401. Signal
HPIBS selects the HP-IB function, LRTCS selects the real time
clock, LGAS selects the key board, interface and display controller
(KID U30l) and signal LDBS selects the device bus interface
(schematic lE).
This information deals with schematic lE.
Display jKeyboardjlnterrupt Interface
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Interrupts
Gate array U60l controls interrupts, and the display and the
keyboard. Interrupts arriving on IDO to IDll cause signal LINTR
to go low. This forces the microprocessor to jump into a interrupt
service routine. The processor reads from the data bus which signal
Theory of Operation 1-3
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