OptiX OSN 8800/6800/3800
Hardware Description
Huawei Proprietary and Confidential
Copyright © Huawei Technologies Co., Ltd.
CLK2:
clock
signal
input
and
output
interfac
es
same functions as the CLK1
and CLK2 interfaces on the
TN52STI board.
of front panel
(H x W x D):
80 mm (3.1
in.) x 50.8
mm (2.0 in.)
x 220 mm
(8.7 in.)
Weight: 0.4
kg (0.88 lb.)
Power
consumption:
Typical
power
consumption
(W): 3 W
Maximum
power
consumption
(W)
b
: 3 W
TOD1-
TOD2:
time
signal
input
and
output
interfac
e
The two interfaces have the
same functions as the TOD1
and TOD2 interfaces on the
TN52STI board.
Phone:
orderw
ire
phone
interfac
e
a: Two DIP switches are present on the TN51EFI1 board for setting the subrack ID. For details, see DIP
Switches on the TN51EFI1 Board.
b: The maximum power consumption is the power consumed by the board when it works normally under the
highest ambient temperature.
DIP Switches on the TN51EFI1 Board
The EFI2 board is connected to the master subrack through the ETH1, ETH2, or ETH3
interface. The ID of each subrack is set by using two DIP switches on the EFI1 board. The
value that can be set by using each of the two DIP switches on the EFI1 board is a binary
value 0 or 1. ID1-ID4 correspond to bits 1-4 of SW2, and ID5-ID8 corresponding to bits 1-4
of SW1. Among these ID values, only ID1-ID5 are valid. ID6-ID8 are reserved. The bits from
high to low are ID5-ID1, by which a maximum of 32 states can be set. The value is 00000 by
default. "0" indicates the master subrack. The other values indicate slave subracks. Figure 4-3
shows the position of the DIP switches on the EFI1 board.
The two DIP switches are numbered SW1 and SW2 and are located to the right of the
CPLD.
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