AFE1_AFE2-1:1
54
Technical specifications
IAR Debug Probes User Guide
I-jet®, I-jet Trace, and I-scope™
● Minimize crosstalk
Keep all high-speed (fast rise and fall times) signals away from other signals to
minimize crosstalk. Take special care of the TRACECLK signal.
● Minimize signal skew
Keep the individual trace port track lengths to be within 0.5 inches (12.5mm) of each
other.
● Match impedance
Make the trace signal impedance 50 Ohm to match the impedance of the debug
connectors and the debug probes
● Minimize signal vias and avoid track stubs.
They might cause impedance mismatch, signal reflections, and distortions.
● Avoid trace pin multiplexing
Multiplexing of the trace pins with other functions increases track lengths and adds
capacitance and inductance and should be avoided. If multiplexing is required, the
designer should add jumpers to disconnect the trace pins from the other logic in case
the tracing signals are too distorted to function properly.
● Use ground and power planes
Using ground and power planes not only helps with power distribution, but also gives
the high-speed signals the shortest return path to ground, which results in less signal
loss. They also make the trace impedance matching easier and more consistent.
Trace signal requirements
I-jet Trace supports DDR (Double Data Rate) clocking mode, which means the data is
output on both edges of the TRACECLK signal. To compensate for variations in MCU
ETM logic and target board PCB layouts, I-jet Trace contains logic to delay the
TRACECLK and each TRACEDATA signal for up to 2.5 ns in 78 ps steps. This logic is
used to synchronize all trace data lines with the trace clock automatically to get the
optimum trace data collection.
Data setup and hold
The following graph and table show the minimum setup and hold timing requirements
of the trace signals with respect to TRACECLK. These timings are fixed by the MCU
manufacturers, and might differ substantially from the data below, so are given as an
example only.
To Next Page
Loading...