174 IBM Power 770 and 780 (9117-MMD, 9179-MHD) Technical Overview and Introduction
PCI adapters are generally complex designs involving extensive on-board instruction
processing, often on embedded microcontrollers. They tend to use industry-standard grade
components with an emphasis on product cost that is relative to high reliability. In certain
cases, they might be more likely to encounter internal microcode errors or many of the
hardware errors described for the rest of the server.
The traditional means of handling these problems is through adapter internal-error reporting
and recovery techniques, in combination with operating system device-driver management
and diagnostics. In certain cases, an error in the adapter can cause transmission of bad data
on the PCI bus itself, resulting in a hardware-detected parity error and causing a global
machine check interrupt, eventually requiring a system reboot to continue.
PCI-enhanced error-handling-enabled adapters respond to a special data packet that is
generated from the affected PCI slot hardware by calling system firmware, which examines
the affected bus, allows the device driver to reset it, and continues without a system reboot.
For Linux, enhanced error handling (EEH) support extends to the majority of frequently used
devices, although various third-party PCI devices might not provide native EEH support.
To detect and correct PCIe bus errors, POWER7+ processor-based systems use CRC
detection and instruction retry correction. For PCI-X, it uses ECC.
Figure 4-7 shows the location and mechanisms used throughout the I/O subsystem for
PCI-enhanced error handling.
Figure 4-7 PCI-enhanced error handling
PCIe
Adapter
PCI-X
Adapter
Parity error
Parity error
I/O drawer concurrent add
CRC with
retry or ECC
PCI Bridge Enhanced
Error Handling
PCI-X to PCI-X
POWER7
12X Channel
Hub
PCI-X
Bridge
PCI-X
Bridge
POWER7
12X Channel
Hub
12X Channel
PCIe Bridge
GX+ / GX++ bus
adapter
12x channel failover
support
PCI Bus Enhanced Error
Handling
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