Chapter 2. Architecture and technical overview 49
2.2.2 Processor interconnects
The POWER7+ processor uses one memory controller, MC0, to access four DIMMs. The
processor uses two GX++ buses (Figure 2-7).
Figure 2-7 Processor interconnects on 4-socket processor card
Each POWER7+ SCM has two serial EPROMs that contain the module’s vital product data
(VPD).
2.3 Memory subsystem
On the Power 770 and Power 780 servers, each enclosure houses 16 DDR3 DIMM slots. The
DIMM cards for the Power 770 and Power 780 are 96 mm tall, fully buffered, and placed in
one of the 16 DIMM slots on the processor card.
2.3.1 Fully buffered DIMM
Fully buffered DIMM technology is used to increase reliability, speed, and density of
memory subsystems. Conventionally, data lines from the memory controllers have to be
connected to the data lines in every DRAM module. This effect traditionally degrades either
the memory access times or memory density. Fully buffered DIMMs overcome this effect by
implementing an advanced buffer between the memory controllers and the DRAMs with two
independent signaling interfaces. This technique decouples the DRAMs from the bus and
memory controller interfaces, allowing efficient signaling between the buffer and the DRAM.
2.3.2 Memory placement rules
The minimum DDR3 memory capacity for the Power 770 and Power 780 systems is 64 GB of
installed memory, of which 32 GB must be activated.
All the memory DIMMs for the Power 770 and Power 780 are capable of capacity upgrade on
demand and must have a minimum of 50% of its physical capacity activated. For example, the
minimum installed memory for both servers is 64 GB RAM, whereas they can have a
minimum of 32 GB RAM active.
POWER7
chip
B Bus - 8 bytes
2 GX ++ Buses - 4 bytes each
WXZ Buses
8 bytes
4 Memory
channels
POWER7 Chip
M
C
0
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