4 - 3
4-3 PLL CIRCUITS
A PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL output com-
pares the phase of the divided VCO frequency to the refer-
ence frequency. The PLL output frequency is controlled by
the divided ratio (N-data) of a programmable divider.
The PLL circuit contains the VCO circuit (Q50, D38). The
oscillated signal is amplified at the LO (Q6) and buffer (Q5)
amplifiers and then applied to the PLL IC (IC1, pin 6).
The PLL IC contains a prescaler, programmable counter,
programmable divider, phase detector, charge pump, etc.
The entered signal is divided at the prescaler and program-
mable counter section by the N-data ratio from the CPU.
The divided signal is detected on phase at the phase detec-
tor using the reference frequency.
If the oscillated signal drifts, its phase changes from the ref-
erence frequency, causing a lock voltage change to com-
pensate for the drift in the oscillated frequency.
A portion of the VCO circuit is amplified at the LO (Q6) and
buffer (Q4) amplifiers and is then applied to the receive 1st
mixer or transmit pre-drive amplifier circuit via the TX/RX
swtiching diode (D3, D4).
4-4 OTHER CIRCUITS
4-4-1 TONE SQUELCH CIRCUIT
A portion of the detected audio signals from the “DET” line
are passed through the tone filter (Q53). The filtered signal
is then applied to the CPU (IC1, pin 94) via the “CTCIN” sig-
nal, and is compared with the programmed tone signal. The
CPU (IC1) outputs control signals as “CTCC” signal to the
AF mute and AF regulator circuits to open the squelch when
a matched tone signal is received.
The programmed subaudible tone signal is output from the
CPU (IC1, pin 91) directly when transmitting with a tone.
• PLL CIRCUIT
LINE
VCC
CPU5
SW5V
VCO5
PS5
R5
T5
DESCRIPTION
The voltage from the attached battery pack.
Common 5 V converted from the VCC line by the
CPU5 regulator (IC12). The output voltage is
applied to the CPU (IC8), EEPROM (IC7) and
reset IC (IC11).
Common 5 V converted from the VCC line by the
SW5 regulator circuit (Q55, Q57, D39). The out-
put voltage is applied to the T5, R5, PS5 and
VCO5 regulator circuits, D/A convertor (IC10, pin
16), etc.
Common 5 V converted from the SW5V line by
the VCO5 regulator circuit (Q11) using the LO
(Q6) and buffer (Q4, Q5) amplifiers. The VCO5
regulator circuit is controlled by the PSVCO line
from the CPU (IC8, pin 62).
Common 5 V converted from the SW5V line by
the PS5 regulator circuit (Q54) using the analog
switch (IC14, pin 14) and APC controller (Q37).
The PS5 regulator circuit is controlled by the
PS5C line from the CPU (IC8, pin 63).
5 V for receiver circuits converted from the
SW5V line by the R5 regulator circuit (Q21)
using the 2nd IF IC (IC2, pin 4), RF (Q12) and IF
(Q14) amplifiers, etc. The R5 regulator circuit is
controlled by the R5C line from the CPU (IC8,
pin 53).
5 V for the transmitter circuit converted from the
SW5V line by the T5 regulator circuit (Q22) using
the pre-drive amplifier (Q3). The T5 regulator cir-
cuit is controlled by the T5C line from the CPU
(IC8, pin 54).
4-5 POWER SUPPLY CIRCUITS
VOLTAGE LINE
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