TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-84
DSYNC
Synchronize Data
Description
Forces all data accesses to complete before any data accesses associated with an instruction, semantically after
the DSYNC is initiated.
Note:The Data Cache (DCACHE) is not invalidated by DSYNC.
Note:To ensure memory coherency, a DSYNC instruction must be executed prior to any access to an active CSA
memory location.
DSYNC(SYS)
-
Status Flags
Examples
dsync
See Also
ISYNC
C Not set by this instruction.
V Not set by this instruction.
SV Not set by this instruction.
AV Not set by this instruction.
SAV Not set by this instruction.
31
-
28 27
12
H
22 21
-
12 11
-
8 7
0D
H
0