Infineon TriCore TC1.6E - MSUB.H - Packed Multiply-Subtract Q Format; MSUBS.H - Packed Multiply-Subtract Q Format, Saturated

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-239
MSUB.H
Packed Multiply-Subtract Q Format
MSUBS.H
Packed Multiply-Subtract Q Format, Saturated
Description
Multiply two signed 16-bit (half-word) values. Subtract the product (left justified if n == 1) from a signed 32-bit value
and put the result into a 32-bit register. There are four cases of half-word multiplication.
Note that n should only take the values 0 or 1, any other value returns an undefined result. If (n == 1) then 8000
H
* 8000
H
= 7FFFFFFF
H
(for signed 16-bit * 16-bit multiplications only).
MSUB.HE[c], E[d], D[a], D[b] LL, n (RRR1)
32||32 -||- (16U * 16L || 16L * 16L) --> 32||32
sc1 = (D[a][31:16] == 8000
H
) AND (D[b][15:0] == 8000
H
) AND (n == 1);
sc0 = (D[a][15:0] == 8000
H
) AND (D[b][15:0] == 8000
H
) AND (n == 1);
mul_res1 = sc1 ? 7FFFFFFF
H
: ((D[a][31:16] * D[b][15:0]) << n);
mul_res0 = sc0 ? 7FFFFFFF
H
: ((D[a][15:0] * D[b][15:0]) << n);
result_word1 = E[d][63:32] - mul_res1;
result_word0 = E[d][31:0] - mul_res0;
E[c] = {result_word1[31:0], result_word0[31:0]}; // Packed fraction
MSUB.HE[c], E[d], D[a], D[b] LU, n (RRR1)
32||32 -||- (16U * 16L || 16L * 16U) --> 32||32
sc1 = (D[a][31:16] == 8000
H
) AND (D[b][15:0] == 8000
H
) AND (n == 1);
sc0 = (D[a][15:0] == 8000
H
) AND (D[b][31:16] == 8000
H
) AND (n == 1);
mul_res1 = sc1 ? 7FFFFFFF
H
: ((D[a][31:16] * D[b][15:0]) << n);
mul_res0 = sc0 ? 7FFFFFFF
H
: ((D[a][15:0] * D[b][31:16]) << n);
result_word1 = E[d][63:32] - mul_res1;
result_word0 = E[d][31:0] - mul_res0;
E[c] = {result_word1[31:0], result_word0[31:0]}; // Packed fraction
MSUB.HE[c], E[d], D[a], D[b] UL, n (RRR1)
32||32 -||- (16U * 16U || 16L * 16L) --> 32||32
sc1 = (D[a][31:16] == 8000
H
) AND (D[b][31:16] == 8000
H
) AND (n == 1);
sc0 = (D[a][15:0] == 8000
H
) AND (D[b][15:0] == 8000
H
) AND (n == 1);
31
c
28 27
d
24 23
1A
H
18 17
n
16 15
b
12 11
a
8 7
A3
H
0
31
c
28 27
d
24 23
19
H
18 17
n
16 15
b
12 11
a
8 7
A3
H
0
31
c
28 27
d
24 23
18
H
18 17
n
16 15
b
12 11
a
8 7
A3
H
0