TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set Information
V1.0 2013-07
User Manual (Volume 2) 1-13
1.4 Coprocessor Instructions
The TriCore
®
instruction set architecture may be extended with implementation defined, application specific
coprocessor instructions. These instructions are executed on dedicated coprocessor hardware attached to the
coprocessor interface.
The coprocessors operate in a similar manner to the integer instructions, receiving operands from the general
purpose data registers, returning a result to the same registers.
The architecture supports the operation of up to four concurrent coprocessors (n = 0, 1, 2, 3).
Two of these (n = 0, 1) are reserved for use by the TriCore CPU, allowing two (n = 2, 3) for use by the application
hardware.
Figure 1-1 Coprocessor Instructions
Table 1-12 Coprocessor Status Flags
C Not set by this instruction
V Not set by this instruction
SV Not set by this instruction
AV Not set by this instruction
SAV Not set by this instruction
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