TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-227
MOV
Move
Description
Move the contents of either data register D[b] (instruction format RR) or const16 (instruction format RLC), to data
register D[c]. The value const16 is sign-extended to 32-bits before it is moved.
The syntax is also valid with a register pair as a destination. If there is a single source operand, it is sign-extended
to 64-bits. If the source is a register pair the contents of data register D[a] go into E[c][63:32] and the contents of
data register D[b] into E[c][31:0].
MOVD[c], const16 (RLC)
D[c] = sign_ext(const16);
MOVE[c], const16 (RLC)
E[c] = sign_ext(const16);
MOVD[c], D[b] (RR)
D[c] = D[b];
MOVE[c], D[b] (RR)
E[c] = sign_ext(D[b]);
MOVE[c], D[a], D[b] (RR)
E[c] = {D[a], D[b]};
MOVD[15], const8 (SC)
Move the contents of either data register D[b] (instruction format SRR), const4 (instruction format SRC) or const8
(instruction format SC) to either data register D[a] (formats SRR, SRC) or D[15] (format SC). The value const4
is sign-extended before it is moved. The value const8 is zero-extended before it is moved.
31
c
28 27
const16
12 11
-
8 7
3B
H
0
31
c
28 27
const16
12 11
-
8 7
FB
H
0
31
c
28 27
1F
H
20 19
-
18 17
-
16 15
b
12 11
-
8 7
0B
H
0
31
c
28 27
80
H
20 19
-
18 17
-
16 15
b
12 11
-
8 7
0B
H
0
31
c
28 27
81
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0B
H
0
To Next Page
Loading...
