Infineon TriCore TC1.6E - ST.H - Store Half-Word

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-356
ST.H
Store Half-word
Description
Store the half-word value in the 16 least-significant bits of data register D[a] to the half-word memory location
specified by the addressing mode.
ST.Hoff18, D[a] (ABS)(Absolute Addressing Mode)
EA = {off18[17:14], 14b'0, off18[13:0]};
M(EA, halfword) = D[a][15:0];
ST.HA[b], off10, D[a] (BO)(Base + Short Offset Addressing Mode)
EA = A[b] + sign_ext(off10);
M(EA, halfword) = D[a][15:0];
ST.H P[b], D[a] (BO)(Bit-reverse Addressing Mode)
index = zero_ext(A[b+1][15:0]);
incr = zero_ext(A[b+1][31:16]);
EA = A[b] + index;
M(EA, halfword) = D[a][15:0];
new_index = reverse16(reverse16(index) + reverse16(incr));
A[b+1] = {incr[15:0], new_index[15:0]};
ST.H P[b], off10, D[a] (BO)(Circular Addressing Mode)
index = zero_ext(A[b+1][15:0]);
length = zero_ext(A[b+1][31:16]);
EA = A[b] + index;
M(EA, halfword) = D[a][15:0];
new_index = index + sign_ext(off10);
new_index = new_index < 0 ? new_index + length : new_index % length;
Store the half-word value in the 16 least-significant bits of either data register D[a] (instruction format or D[15] to
the half-word memory location specified by the addressing mode.
31
off18[9:6]
28 27
02
H
26 25
off18[13:10]
22 21
off18[5:0]
16 15
off18[17:14]
12 11
a
8 7
25
H
0
31
off10[9:6]
28 27
22
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
89
H
0
31
-
28 27
02
H
22 21
-
16 15
b
12 11
a
8 7
A9
H
0
31
off10[9:6]
28 27
12
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
A9
H
0