Infineon TriCore TC1.6E - SUBS - Subtract Signed with Saturation; SUBS.U - Subtract Unsigned with Saturation

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-373
SUBS
Subtract Signed with Saturation
SUBS.U
Subtract Unsigned with Saturation
Description
Subtract the contents of data register D[b] from the contents of data register D[a] and put the result in data register
D[c]. The operands are treated as signed (SUBS) or unsigned (SUBS.U) 32-bit integers, with saturation on signed
(SUBS) or (SUBS.U) unsigned overflow.
SUBSD[c], D[a], D[b] (RR)
result = D[a] - D[b];
D[c] = ssov(result, 32);
SUBSD[a], D[b] (SRR)
SUBS.UD[c], D[a], D[b] (RR)
result = D[a] - D[b];
D[c] = suov(result, 32);
Status Flags
Subtract the contents of data register D[b] from the contents of data register D[a] and put the result in data
register D[a].The operands are treated as signed 32-bit integers, with saturation on signed overflow.
result = D[a] - D[b];
D[a] = ssov(result, 32);
C Not set by these instructions.
V signed:
overflow = (result > 7FFFFFFF
H
) OR (result < -80000000
H
);
if (overflow) then PSW.V = 1 else PSW.V = 0;
unsigned:
overflow = (result > FFFFFFFF
H
) OR (result < 00000000
H
);
if (overflow) then PSW.V = 1 else PSW.V =0;
SV if (overflow) then PSW.SV = 1 else PSW.SV = PSW.SV;
31
c
28 27
0A
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0B
H
0
15
b
12 11
a
8 7
62
H
0
31
c
28 27
0B
H
20 19
-
18 17
-
16 15
b
12 11
a
8 7
0B
H
0