TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-20
ADDIH
Add Immediate High
Description
Left-shift const16 by 16 bits, add the contents of data register D[a], and put the result in data register D[c]. The
operands are treated as signed integers.
ADDIHD[c], D[a], const16 (RLC)
result = D[a] + {const16, 16’h0000};
D[c] = result[31:0];
Status Flags
Examples
addih d3, d1, -14526
See Also
ADD, ADDC, ADDI, ADDS, ADDS.U, ADDX
C Not set by this instruction.
V overflow = (result > 7FFFFFFF
H
) OR (result < -80000000
H
);
if (overflow) then PSW.V = 1 else PSW.V = 0;
SV if (overflow) then PSW.SV = 1 else PSW.SV = PSW.SV;
AV advanced_overflow = result[31] ^ result[30];
if (advanced_overflow) then PSW.AV = 1 else PSW.AV = 0;
SAV if (advanced_overflow) then PSW.SAV = 1 else PSW.SAV = PSW.SAV;
31
c
28 27
const16
12 11
a
8 7
9B
H
0
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