Infineon TriCore TC1.6E - Page 397

TriCore
®
TC1.6P & TC1.6E
32-bit Unified Processor Core
Instruction Set
V1.0 2013-07
User Manual (Volume 2) 3-350
A[b+1] = {length[15:0], new_index[15:0]};
ST.BA[b], off10, D[a] (BO)(Post-increment Addressing Mode)
EA = A[b];
M(EA, byte) = D[a][7:0];
A[b] = EA + sign_ext(off10);
ST.BA[b], off10, D[a] (BO)(Pre-increment Addressing Mode)
EA = A[b] + sign_ext(off10);
M(EA, byte) = D[a][7:0];
A[b] = EA;
ST.BA[b], off16, D[a] (BOL)(Base + Long Offset Addressing Mode)
EA = A[b] + sign_ext(off16);
M(EA, byte) = D[a][7:0];
ST.BA[b], off4, D[15] (SRO)
ST.BA[b], D[a] (SSR)
ST.BA[b], D[a] (SSR)(Post-increment Addressing Mode)
M(A[b] + zero_ext(off4), byte) = D[15][7:0];
M(A[b], byte) = D[a][7:0];
M(A[b], byte) = D[a][7:0];
A[b] = A[b] + 1;
31
off10[9:6]
28 27
00
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
89
H
0
31
off10[9:6]
28 27
10
H
22 21
off10[5:0]
16 15
b
12 11
a
8 7
89
H
0
31
off16[9:6]
28 27
off16[15:10]
22 21
off16[5:0]
16 15
b
12 11
a
8 7
E9
H
0
15
b
12 11
off4
8 7
2C
H
0
15
b
12 11
a
8 7
34
H
0
15
b
12 11
a
8 7
24
H
0