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Integra DTR-7.9 Service Manual

Integra DTR-7.9
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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -24
Q3551 : ES29LV800ET-70TG (8 Mbit Flash Memory)
BLOCK DIAGRAM
TX-SR806/SA806
Command
Register
Analog Bias
Generator
Address Latch
BYTE#
CE#
OE#
A<0:18>
RESET#
Vcc
Vss
Chip Enable
Output Enable
Logic
Vcc Detector
Timer/
Counter
Y-Decoder
X-Decoder
Y-Decoder
Cell Array
Data Latch/
Sense Amps
Input/Output
Buffers
Sector Switches
DQ0-DQ15(A-1)
RY/BY#
Write
State
Machine
WE
#
w
w
w
.
x
i
a
o
y
u
1
6
3
.
c
o
m
Q
Q
3
7
6
3
1
5
1
5
0
9
9
2
8
9
4
2
9
8
T
E
L
1
3
9
4
2
2
9
6
5
1
3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com

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Integra DTR-7.9 Specifications

General IconGeneral
BrandIntegra
ModelDTR-7.9
CategoryReceiver
LanguageEnglish

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