Integra DTR-7.9 Service Manual

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -26
Q3461, Q3561 : IS42S32200E-6TL (64 Mbit SD RAM)
BLOCK DIAGRAM
TX-SR806/SA806
CLK
CKE
CS
RAS
CAS
WE
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
A10
COMMAND
DECODER
&
CLOCK
GENERATOR
MODE
REGISTER
REFRESH
CONTROLLER
REFRESH
COUNTER
SELF
REFRESH
CONTROLLER
ROW
ADDRESS
LATCH
MULTIPLEXER
COLUMN
ADDRESS LATCH
BURST COUNTER
COLUMN
ADDRESS BUFFER
COLUMN DECODER
DATA IN
BUFFER
DATA OUT
BUFFER
DQM0-3
DQ 0-31
V
DD/VDDQ
GND/GNDQ
11
11
11
11
32
32 32
32
256
(x 32)
2048
2048
2048
ROW DECODER
2048
MEMORY CELL
ARRAY
BANK 0
SENSE AMP I/O GATE
BANK CONTROL LOGIC
ROW
ADDRESS
BUFFER
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL 13942296513 QQ 376315150 892498299 TEL 13942296513 QQ 376315150 892498299
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Integra DTR-7.9 Specifications

General

Brand	Integra
Model	DTR-7.9
Category	Receiver
Language	English