Intel Agilex I Series User Manual

The following sections describe the Clock Controller buttons.
Read
Reads the current frequency setting for the oscillator associated with the active tab.
Default
Sets the frequency for the oscillator associated with the active tab back to its default
value. This can also be accomplished by power cycling the board.
Set
Sets the programmable oscillator frequency for the selected clock to the value in the
OUTx output controls for the Si5391. Frequency changes might take several
milliseconds to take effect. You might see glitches on the clock during this time. Intel
recommends resetting the FPGA logic after changing frequencies.
Import
Si5391 has a two-time writable non-volatile memory (NVM). You can generate the
register list from the Clockbuilder Pro tool and import it into Si5391 to update the
settings of the NVM. Register changes are volatile after power cycling.
Clockbuilder Pro Software on Skyworks website
4.4. Monitor On-board Power Regulator through Power Monitor GUI
The Power Monitor GUI reports most power rails’ voltage, current, and power
information on the board. It also collects temperature from FPGA die, power modules,
and diodes assembled on PCB.
Power Monitor GUI communicates with System Intel MAX 10 through either USB port
J8 or 10-pin JTAG header J10. System Intel MAX 10 monitors and controls power
regulator, temperature/voltage/current sensing chips through a 2-wire I
2
C bus.
The instructions to run Power Monitor GUI are stated in the Run BTS GUI on page 24.
It can also be started with the BTS GUI icon “Power”.
Note: You cannot run the stand-alone Power Monitor GUI when the BTS or the Clock
Controller GUI is running at the same time.
4. Board Test System
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I-Series FPGA Development Kit User Guide
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Intel Agilex I Series Specifications

General

Brand	Intel
Model	Agilex I Series
Category	Microcontrollers
Language	English

Summary

1. Overview

1.2. Box Contents

1.3. Operating Conditions

Specification of the recommended environmental and operational parameters for the development kit.

2. Getting Started

2.1. About Intel Quartus Prime Software

2.3. Installing the Intel FPGA Download Cable II Driver

3. Development Board Setup

3.1. Applying Power to the Development Board

Detailed steps for powering the development board in both PCIe-compliant and bench-top modes.

3.2. Default Switch and Jumper Settings

Explanation of the board's switch and jumper configurations and their functions.

3.3. How to Generate a POF Image to Program the Flash

Procedure for creating a Programmer Object File (.pof) for programming the flash memory.

3.4. How to Program the Generated POF Image

Step-by-step instructions for programming the generated POF image onto the development board.

3.5. The Required SmartVID QSF Assignments to Compile a Design

Necessary SmartVID QSF settings in Quartus Prime for successful design compilation.

4. Board Test System

4.1. Set Up BTS GUI Running Environment

Guide to setting up the Java environment and installing necessary components for the Board Test System.

4.1.1. Download OpenJDK

Instructions for downloading the Temurin OpenJDK, a prerequisite for the Board Test System.

4.1.2. Download OpenJFX

4.1.3. Install OpenJDK and OpenJFX

4.1.4. Run BTS GUI

4.2. Test the Functionality of the Development Kit

Overview of using the Board Test System GUI to test various functionalities of the development kit.

4.2.2. The Configure Menu

4.2.4. The GPIO Tab

4.2.5. The XCVR Tab

Performing transceiver tests, including QSFPDD, using the XCVR tab in the BTS GUI.

4.2.5.1. The QSFPDD NRZ Tab

4.2.5.2. The QSFPDD PAM4 Tab

4.2.6. The RAM Tab

4.3. Control On-board Clock through Clock Controller GUI

How to adjust on-board programmable PLL frequencies using the Clock Controller GUI.

4.4. Monitor On-board Power Regulator through Power Monitor GUI

Using the Power Monitor GUI to observe voltage, current, and temperature data.

4.5. BTS Test Areas

4.6. Identify Test Pass or Fail-based on BTS GUI Test Status

A. Development Kits Components

A.3. PCIe and CXL Interfaces

A.8. FPGA Configuration

Step-by-step guide on configuring the FPGA using the Intel Quartus Prime Programmer.

A.9. Supported Configuration Modes

A.10. Memory Interfaces

A.13. System Power

Comprehensive overview of the development board's power supply system and operating modes.

A.14. Temperature Monitoring

B. Additional Information

B.1. Safety and Regulatory Information

Essential safety, regulatory, and compliance information required for using the development kit.

B.2. Compliance Information