Intel Agilex I Series - A.9. Supported Configuration Modes

Programming the FPGA over Intel FPGA Download Cable II
Figure 34 on page 48 shows the high-level conceptual block diagram for
programming the FPGA over the embedded Intel FPGA Download Cable II or external
download cable.
A.9. Supported Configuration Modes
• The development board supports two configuration modes: Avalon-ST (AVST) x8
and JTAG.
• The default configuration is AVST x8 using a 2Gb QSPI flash device.
• JTAG configuration is supported by using either the embedded Intel FPGA
Download Cable II or the Intel FPGA Download Cable II dongle.
Avalon-ST (AVST) x8 Mode
The SDM block in the Intel Agilex device controls the configuration process and
interface. The Intel MAX 10 System Controller (U34) interfaces to the Intel Agilex
FPGA in the AVST x8 mode. The Intel MAX 10 also interfaces to the QSPI flash in the
active serial (AS) x4 mode. For the AS x4 mode, MSEL[2:0] configuration pin
strapping (SW2) must be set to [110]. The flash device is Micron Technology 1.8V
core, 1.8V I/O 2 Gigabit CFI NOR-type device (P/N: MT25QL02GBB8E12-0).
JTAG Configuration Mode
The JTAG switch implemented in the Intel MAX 10 System Controller (U34) allows the
selection of devices to be included in the JTAG chain. It is done by the settings of the
DIP switch SW5. The embedded Intel FPGA Download Cable II (or external download
cable) or PCIe JTAG can be selected as the source for programming the devices on the
chain. The embedded Intel FPGA Download Cable II is the default setting for this
configuration mode.
A. Development Kits Components
683288 | 2022.09.22
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I-Series FPGA Development Kit User Guide
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