System Event Log Troubleshooting Guide for EPSD
Platforms Based on Intel
®
Xeon
®
Processor E5 4600/2600/2400/1600/1400 Product Families
Processor Subsystem
Revision 1.1 Intel order number G90620-002 59
6. Processor Subsystem
Intel
®
servers report multiple processor-centric sensors in the SEL.
6.1 Processor Status Sensor
The BMC provides an IPMI sensor of type processor for monitoring status information for each processor slot. If an event state
(sensor offset) has been asserted, it remains asserted until one of the following happens:
A rearm Sensor Events command is executed for the processor status sensor.
AC or DC power cycle, system reset, or system boot occurs.
CPU Presence status is not saved across A/C power cycles and therefore will not generate a deassertion after cycling AC power.
Table 47: Process Status Sensors Typical Characteristics
70h = Processor 1 Status
71h = Processor 2 Status
72h = Processor 3 Status
73h = Processor 4 Status
Event Direction and
Event Type
[7] Event direction
0b = Assertion Event
1b = Deassertion Event
[6:0] Event Type = 6Fh (Sensor Specific)
[7:6] – 00b = Unspecified Event Data 2
[5:4] – 00b = Unspecified Event Data 3
[3:0] – Event Trigger Offset as described in Table 48
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