Power Subsystems
System Event Log Troubleshooting Guide for EPSD
Platforms Based on Intel
®
Xeon
®
Processor E5 4600/2600/2400/1600/1400 Product Families
34 Intel order number G90620-002 Revision 1.1
If the SystemPowerGood signal has not asserted by the time the VR Watchdog Timer expires, the FW powers down the system,
logs a SEL entry, and emits a beep code (1-5-1-2). This failure is termed as VR Watchdog Timeout.
Table 14: Voltage Regulator Watchdog Timer Sensor Typical Characteristics
Event Direction and
Event Type
[7] Event direction
0b = Assertion Event
1b = Deassertion Event
[6:0] Event Type = 03h (“digital” Discrete)
[7:6] – 00b = Unspecified Event Data 2
[5:4] – 00b = Unspecified Event Data 3
[3:0] – Event Trigger Offset = 1h = State Asserted
4.2.1 Voltage Regulator Watchdog Timer Sensor – Next Steps
1. Ensure that all the connectors from the power supply are well seated.
2. Cross test the baseboard. If the issue remains with the baseboard, replace the baseboard.
4.3 Power Unit
The power unit monitors the power state of the system and logs the state changes in the SEL.
4.3.1 Power Unit Status Sensor
The power unit status sensor monitors the power state of the system and logs state changes. Expected power-on events such as DC
ON/OFF is logged and unexpected events are also logged, such as AC loss and power good loss.