DR600 Service Manual
programming cannot be completed, changing NAND FLASH (U7)
for a second modulation and changing the parameter settings is
suggested.
2. Check the DC power supply of the processor unit below:
3V3_OMAP
1V2_OMAP
1V8_DDR
3. Check the DC power supply of the FPGA unit below.
VCCINT(1.2V)
VCCD_PLL(1.2V)
VCCA(2.5V)
VCCIO(3.3V)
4. Check the baseband board 12.8M clock (Y5) and 24M
clock(Y2).
11
Network connection
Fails
1. Check the cable connecting status.
2. Check the internet card chip power.
3. Check the 50M clock of the internet card chip.
12 No voice repeated
Please check Pin2 of transmit unit connector (J17). If there is no
modulation signal, please check reference voltage VREF (2.048V)
of DAC output from U29. If the VREF voltage is abnormal, please
change U29. If VREF is normal, please check DAC (U24).
13
No voice outside the
mode.
1. Check the connecting status of ACCY connecting cable and
connector (U9).
2. Check the 18.432MHz clock of CODEC and power of 3VE_A,
3V3_OMAP. Please input 1KHz and 50mV testing audio signal on
the TXAF test point of baseband board, and check the transmitting
deviation from Comprehensive test instrument. If the deviation is
abnormal, please change CODEC chip (U30).
14
Abnormal
Programming
1. Check the connecting status of network connector (J12) and
network cable.
2. Check the network card running status of PC.
3. Check 50M clock(J23) of network connector on baseband.
4. Check prompt content on the programming running print
information and make the corresponding judgment.
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