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Lattice iCE40 - Test Points; Figure 9.1. J6 Header a Breakouts; Figure 9.2. J7 Header B Breakouts; Figure 9.3. J5 PMOD Connector

Lattice iCE40
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iCE40 Ultra Breakout Board
Evaluation Board User Guide
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02034-1.2 11
9. Test Points
The board features a number of headers and test connections which provide access to the iCE40 Ultra I/O:
Figure 9.1. J6 Header A Breakouts
Figure 9.2. J7 Header B Breakouts
Figure 9.3. J5 PMOD Connector