Lattice iCE40 - Ordering Information; Table 12.1. Ordering Information

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iCE40 Ultra Breakout Board

Evaluation Board User Guide

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

18 FPGA-EB-02034-1.2

12. Ordering Information

Table 12.1. Ordering Information

Description

Ordering Part Number

China RoHS Environment-Friendly

Use Period (EFUP)

iCE40 Ultra Breakout Board

ICE5LP4K-B-EVN

Main Page

Table of Contents3
Acronyms in this Document5
Introduction6
Features6
Figure 2.1. Top Side of the Ice40 Ultra Breakout Board7
Ice40 Ultra Device8
Software Requirements8
Demonstration Design Shunts8
Figure 5.1. Default Shunt Locations8
Clock Sources9
Board Power9
Board Configuration and Programming10
Figure 8.1. Configuration and Programming Details10
Test Points11
Figure 9.1. J6 Header a Breakouts11
Figure 9.2. J7 Header B Breakouts11
Figure 9.3. J5 PMOD Connector11
Figure 9.4. J7 Header B Breakouts12
Figure 9.5. Breakout Headers12
RGB LED Demonstration Design and User Interface13
Figure 10.1. SPI Flash Selection for J10 (Vertical)13
Figure 10.2. Ice40 Ultra Selection for J10 (Horizontal)13
Figure 10.3. Ice40 Ultra LED Demonstration Interface14
User Interface Serial Communication Interface15
LED Control through SPI15
SPI Protocol15
Register Definitions15
Figure 11.1. SPI Physical Transaction15
Table 11.1. ADDR [7:0]15
Table 11.2. REG [15:0]15
Table 11.3. RGB Color [3:0]15
Table 11.4. Brightness [3:0]16
Table 11.5. Breathe Ramp [3:0]16
Table 11.6. Blink Rate [3:0]17
Ordering Information18
Table 12.1. Ordering Information18
Technical Support Assistance19
Appendix A. Schematic Diagrams20
Figure A.1. Block Diagram20
Figure A.6. SPI20
Figure A.2. FTDI Connection21
Figure A.3. DUT Connection22
Figure A.4. Leds and Headers23
Figure A.5. Regulator Connection24
Appendix B. Bill of Materials26
Revision History29

Lattice iCE40 - Ordering Information; Table 12.1. Ordering Information

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