Marantz SR8001 - Page 132

166
IC63 : CD0040AF
MPU Interface
Timing Generator
Input
Interface
Video Processing Engine
SDRAM Interface
MPEG2 Video Decoder
or
Digital Video Decoder
MPU
SDRAM
Digital Out
Configuration Registers
Fig. 2-1: System Block Diagram
ovdd ovss TEST4 TEST3 WE MCLK CAS DQM RAS ovss ovdd MA9 MA11 MA8 MA10 ovdd cvss TEST5 ovss MA7 MA0 MA6 MA1 ovss ovdd MA5 MA2 MA4 MA3 ovss ovdd MD16 MD17 MD18 MD19 ovdd
108 107 106 105 104 103 102 101 100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
cvdd 109 72 ivdd
MD7 110 71 cvdd
MD8 111 70 ovss
MD6 112 69 RFFI
MD9 113 68 FILM
ovdd 114 67 CO9
ovss 115 66 CO8
MD5 116 65 CO7
MD10 117 64 CO6
MD4 118 63 CO5
MD11 119 62 ovss
ovdd 120 61 ovdd
ovss 121 60 CO4
MD3 122 59 CO3
MD12 123 58 CO2
MD2 124 57 CO1
MD13 125 56 CO0
ovss 126 55 ovss
cvss 127 54 cvss
ovdd 128 53 ovdd
MD1 129 52 YO0
MD14 130 51 YO1
MD0 131 50 YO2
MD15 132 49 YO3
SLV 133 48 YO4
RFFO 134 47 ovss
SDA 135 46 ovdd
SCL 136 45 YO5
SRN 137 44 YO6
ovss 138 43 YO7
cvdd 139 42 YO8
PLL
_
VDD 140 41 YO9
VPDX 141 40 CLKO
TEST6 142 39 TEST2
PLL
_
GND 143 38 TEST1
ivdd 144 37 cvdd
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
ovdd
CLKI
TEST7
PLL_EN
PI0 PI1 PI2 PI3 PI4 PI5 PI6 PI7 PI8 PI9
NHSI
NVSI
ovss
THRM
cvss
NVSO
NHSO
PO9 PO8 PO7 PO6
ovdd
ovss
PO5 PO4 PO3 PO2 PO1 PO0
TEST0
ovss
ovdd
Pin Assignment
of
CD0040AF