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7 FUNCTIONS
7.1 Cyclic Transmission
Input and output status when failure occurs
This section describes the status of input from a data link faulty station and output status of cyclic data if a stop error occurs in
the CPU module.
Output status for CPU STOP
The following are cyclic data outputs when the CPU module is in the STOP state.
• MELSEC iQ-R, MELSEC-Q/L: Data is held. However, when the device set to perform link refresh is Y device, the data is
cleared.
• MELSEC iQ-F: Data is cleared.
Status Operation
Input status from data link faulty station RX is cleared. Regarding RWr, the data before an error occurs is held.
Cyclic data output when a stop error occurs in the CPU module • MELSEC iQ-R, MELSEC-Q/L: Data is held.
• MELSEC iQ-F: Data is cleared.
: Area where the input from a faulty station is cleared
: Area where the operation (clear/hold) differs depending on the CPU module
: Area where data is held
: Area where the operation depends on the settings on the slave station side
RX
RWw
RWr
RY
RX
RWw
RWr
RY
RX
RWw
RWr
RY
RX
RWw
RWr
RY
Slave station 2Slave station 1
Master station
Slave station 3
Slave station 1
Slave station 2
Slave station 3
Slave station 1
Slave station 2
Slave station 3
Slave station 1
Slave station 2
Slave station 3
Slave station 1
Slave station 2
Slave station 3
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