Mitsubishi Electric Q26UD(E)HCPU - Page 528

526
SD241
Extension
stage
number
0: Main
base
only
1 to 7:
Number
of
extensio
n base
units
This register stores the maximum number of extension base
units installed.
S (Initial) New
QCPU
Number of
extension
blocks
0: Main
only
1 to 3:
Number
of
extensio
n blocks
This register stores the maximum number of connected
extension blocks.
LCPU
*9
SD242
A/Q base
differentiation
Base type
differentiation
0: QA**B
is
installed
(A
mode)
1: Q**B is
installed
(Q
mode)
S (Initial) New
Qn(H)
QnPH
QnPRH
Installed Q
base
presence/a
bsence
Base type
differentiation
0: Base
not
installed
1: Q**B is
installed
Q00J/Q00/Q01
A/Q base
differentiation
Base type
differentiation
0:
QA1S**
B,
QA1S6
ADP+A
1S*B,
QA**B,
and
QA6AD
P+ A**B
are
installed
/ Base
not
installed
1: Q**B is
installed
• For the Q00UJCPU, the bits for the third to seventh
extension bases are fixed to "0".
• For the Q00UCPU, Q01UCPU, and Q02UCPU, the bits for
the fifth to seventh extension bases are fixed to "0".
QnU
Number Name Meaning Explanation
Set by
(When Set)
Corresponding
ACPU
D9
Corresponding
CPU
b0b1b2b7
to
Fixed to 0
Main base unit
1st extension base
2nd extension base
to
7th extension base
Fixed to 0
when the
base is not
installed.
b0b1b2b4
Fixed to 0
Main base unit
1st extension base
2nd extension base
4th extension base
to
to
b0b1b2b7
to
Fixed to 0
Main base unit
1st extension base
2nd extension base
to
7th extension base
Fixed to 0
when the
base is not
installed.